Upcoming Events

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IXPUG Working Groups 

April 12, 2018


"Topology and Cache Coherence in Knights Landing and Skylake Xeon Processors”

Intel's second-generation Xeon Phi (Knights Landing) and Xeon Scalable Processor ("Skylake Xeon") are both based on a new 2-D mesh architecture with significant changes to the cache coherence protocol. This talk will review some of the most important new features of the coherence protocol (such as "snoop filters", "memory directories", and non-inclusive L3 caches) from a performance analysis perspective. 


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IXPUG Workshop at KAUST

April 22-25, 2018 

Thuwal, Saudi Arabia 

 This meeting is hosted by King Abdullah University of Science and Technology (KAUST) the IXPUG Conference will focus on the areas of energy, climate simulations and analytics based on PDE’s or analytics based on geospacial statistics are limited to memory, processing or both.  This is the first IXPUG meeting in the Middle East.


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IXPUG2016 SmallGroup xs

IXPUG Working Groups 

May 10, 2018


"High Productivity Languages"

This session addresses challenges of numerical analysis and simulations at scale through tools, such as Python, which are often used for prototyping are not designed to scale to large problems. Covering a brief overview of scalability aspects with respect to modern hardware architecture we will characterize what the problem at scale is, its inherit characteristics and how these map onto software design choices. 


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IXPUG Workshop at ISC 

June 28, 2018

 "Many-core Computing on Intel Processors: Applications, Performance and Best-Practice Solutions" 

This one full-day IXPUG workshop will bring together software developers and technology experts to share challenges, experiences and best-practice methods ,for the optimization of HPC, Machine Learning (ML) and Data Analytics (DA) workloads on Intel Xeon Scalable Processors and Intel Xeon Phi Processors.




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IXPUG Annual Fall Conference

Hosted by Sandia National Laboratories & Los Alamos National Lavatory

September 25-28, 2018

Oregon, US

The Intel eXtreme Performance Users Group (IXPUG) is an active community led forum for sharing industry best practices, techniques, tools, etc. for maximizing efficiency on Intel platforms and products. This meeting will focus on all aspects of employing, adopting many-core processing technologies and techniques for optimal application execution.


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Previous Events

IXPUG Working Groups

March 8, 2018


"Compiler Prefetching for Knights Landing"
We will cover some of the recent changes in the compiler-based prefetching (for Knights Landing and Skylake) and provide tips on how to tune for performance using compiler prefetching options, pragmas and prefetch intrinsics. 

See Archived webcast


IXPUG Annual Spring Conference

Hosted by CINECA

March 5-7, 2018

Bologna, Italy

The Intel eXtreme Performance Users Group (IXPUG) is an active community led forum for sharing industry best practices, techniques, tools, etc. for maximizing efficiency on Intel platforms and products. This meeting will focus on all aspects of employing and adopting manycore processing technologies and techniques for optimal application execution.


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IXPUG Working Groups

February 8, 2018


"Threading Building Blocks (TBB) Flow Graph: Expressing and Analyzing Dependencies in Your C++ Application"

Developing for heterogeneous systems is challenging because applications may be composed of many layers of parallelism and employ a diverse set of programming models or libraries. This session focuses on Flow Graph, an extension to the Threading Building Blocks (TBB) interface that can be used as a coordination layer for heterogeneity that retains optimization opportunities and composes with existing models. Finally, we validate this approach by presenting use cases of applications using Flow Graph.


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 IXPUG Workshop at HPC Asia Conference 

January 28-31, 2018 

Tokyo, Japan

The Intel eXtreme Performance Users Group (IXPUG) is an active community led forum for sharing industry best practices, techniques, tools, etc. for maximizing efficiency on Intel platforms and products. This is a half day workshop with contributed papers and key note talks. Any research aspect related to Intel Xeon Phi is welcome to present to share this advanced technology for high performance computing.


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IXPUG Working Groups

January 11, 2018

Virtual (GoToMeeting)

"Vectorization of Inclusive/Exclusive Scan in Compiler 19.0"
We propose a new OpenMP syntax to support inclusive and exclusive scan patterns. The proposal defines several new constructs to support inclusive and exclusive scans through OpenMP, defines semantics for these constructs and possible combination of parallelization and vectorization.

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Usability, Scalability and Productivity on
Many-Core Processors: Intel Xeon Phi and Beyond

Presentations posted!

Tuesday, November 14, 5:15pm 

Room 603 



Intel® HPC Developer Conference 2017

The Intel® HPC Developer Conference 2017 features industry luminaries sharing best practices and techniques to help realize the potential of these technologies. Attendees will gain hands-on experience with Intel platforms, network with peers and industry experts, and gain insight on recent technology advances to maximize software efficiency that help drive discovery.

IXPUG is a sponsor of this event. We hope to see you there!





2017 IXPUG US Annual Meeting

 September 26-28, 2017


The IXPUG US-based Annual Meeting this year is hosted by the Texas Advanced Computing Center (TACC) in Austin, TX.

 This meeting will focus on all aspects of employing and adopting manycore processing (KNL/KNC) technologies and techniques for optimal application execution. 

Presentations, keynotes, a panel discussion, and a roadmap will provide details on discoveries, experiences, methods, and the future for  efficient and scalable manycore computing.  There will also be hands-on KNL training tutorials,  designed for both beginners and intermediate-level users.

 Did you attend this event? Please fill out the event survey


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IXPUG Workshop: "Experiences on Intel Knights Landing at the One Year Mark"

June 22, 2017 

This one full-day IXPUG workshop at ISC 2017 is about sharing ideas, implementations, and experiences that will help users take advantage of new Intel Xeon Phi features, such as AVX512 and high-bandwidth MCDRAM memory, as well as relevant high-performance system fabrics on large-scale KNL-based systems (e.g. OmniPath). 




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IXPUG "Birds of a Feather" (BOF) at ISC: Achieving Performance on Large-Scale Intel Xeon Phi Knights Landing Systems

June 19, 2017

This BOF, conducted by leaders of the 500+ member Intel eXtreme Performance Users Group (IXPUG), seeks to build and strengthen a community among those developing HPC applications for large-scale systems incorporating Intel Xeon Phi processors and co-processors.

Draft agenda now available!


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IXPUG Russia Annual Meeting 

June 1-2

Hosted by the Joint Supercomputer Center of the Russian Academy of Sciences, Moscow

Intel annually holds an International conference IXPUG Russia (Intel eXtreme Performance Users Group). We will hold the event to share experience in practical issues of development and debugging multi-threaded applications on multi-core processors Intel® Xeon Phi™. The focus of this year will be dedicated to the user experience on Intel® Xeon Phi™ 2nd generation (Knights Landing).


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IXPUG Software-Defined Visualization Workshop

Hosted by the Texas Advanced Computing Center 

May 22-25, 2017

This four-day event is aimed at simulation developers and domain experts with simulation implementation expertise. After an initial orientation to in-situ capabilities, the workshop will combine domain expert attendees with visualization experts from TACC, Kitware, and Intel to design and implement a proof-of-concept in-situ visualization for each attendee's simulation. The workshop will provide a functional prototype on which to continue in-situ development, as well as identifying barriers to in-situ analysis for particular scientific domains.

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IXPUG Annual Spring Meeting

Hosted by the University of Cambridge, UK

April 10-13, 2017

Hosted by the The Stephen Hawking Centre for Theoretical Cosmology (CTC) at the University of Cambridge, the IXPUG Annual Spring Conference 2017 will feature presentations and tutorials. Application performance and scalability challenges at all levels will be covered, including  application tuning on large KNL systems.

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SC’16 Bird of Feather (BoF): “Optimizing Performance on Intel® Xeon Phi and Beyond: Unleashing the Power of Many-Core Processors”

November 16, 2016  12:15pm, Room 355-F

This IXPUG BoF will provide a forum for application and tool developers, HPC center staff, and Intel experts to discuss their early successes and challenges. This BOF will showcase successes in modernizing code for KNL and beyond, highlighting tuning methodologies, tools features, and real-world impact and community codes. IXPUG is an independent users group for anyone interested in application performance on the Intel Xeon Phi.


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Intel® HPC Developer Conference

November 12-13, 2016, Sheraton Salt Lake City Hotel

Join high performance computing (HPC) experts at the 2016 Intel® HPC Developer Conference, November 12-13 in Salt Lake City! This free event brings together architecture experts and developers to discuss, share and highlight the latest in supercomputing. Get technical and hands-on knowledge, learn from real world examples, and gain insights about future technologies from industry leaders. Register Today!


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2016 IXPUG US Annual Meeting

September 19-22, 2016

This IXPUG US-based annual meeting is a combination of tutorials, workshops, and plenary presentations featuring case studies around optimization work on open source codes by various community experts. This event will be hosted by Argonne National Laboratory in Lemont, Illinois.




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ISC’16 Workshop: “Application Performance on Intel Xeon Phi – Being Prepared for Knights Landing and Beyond”

June 23, 2016

The workshop brought together software developers and technology experts to share challenges, experiences and best-practice methods for the optimization of HPC workloads on the Intel Xeon Phi. The workshop will cover application performance and scalability challenges at all levels - from single processor, to moderately-scaled cluster, up to large HPC configurations with many Xeon Phi devices.


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ISC’16 Birds of Feather (BoF): “Gearing Up Application Performance for Intel Xeon Phi (KNL) Supercomputers”

June 22, 2016

The IXPUG BoF event showcased a Knights Landing demo, featuring the Intel Xeon Phi™ Processor based Ninja Developer Platform hardware. Community led presentations on cases studies from the IXPUG Monthly Working Groups, Lightning Talks, Tools Talks and discussions to present performance for selected benchmarking cases.


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TACC Knights Landing Tutorial

June 18, 2016

Texas Advanced Computing Center (TACC) partnered with Intel Corp. to offer a tutorial to Intel Xeon Phi program developers. The training provided hands-on exercises that were executed on the Stampede Knights Landing system at TACC.



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2016 IXPUG Russia Annual Meeting

June 9-10, 2016

The IXPUG Russia event was hosted by Saint-Petersburg Polytechnic University. This workshop and tutorial sessions addressed key applications from the end user and developers’ perspective, case studies, roundtable discussions. Attendance from Russia community experts, sharing learnings with the broader HPC developers and includes an academic teaching session.


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2016 IXPUG Europe Annual Meeting

March 14-18, 2016

This event was a combination of a workshop, tutorial and community networking and shared learnings, etc. Host by IT4Innovations National Supercomputing Centre. Included workshops, tutorials and code dungeon address a wide range of optimization technics, teaching materials, etc.



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SC15 Birds of a Feather

November 18, 2015

This Birds of a Feather supported SC15 in giving attendees insight into how we are paving the way for Performance on Intel® Knights Landing Processors and beyond: Unleashing the Power of Next-Generation Many-Core Processors. We had approximately 180 participants.



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2015 IXPUG US Annual Meeting

September 28-October 2, 2015

The IXPUG annual meeting is a forum where the broader community of Intel Xeon Phi users can share best practices, optimization approaches and results. There were hands-on tutorials, keynote and general presentations, optimization workshops, libraries and program models, deep dive code dungeon showcasing real time case study project work.


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ISC'15 Bird of Feather: "Unleashing the Power of Next-Generation Many-Core Processors”

July 15, 2015

The Birds of Father (BoF) covers insight to Intel Xeon Phi (Knights Landing) architecture, monthly public optimization forums, leveraging Intel Software tools, Lightning Talks from the broader community, various Tool Talk Discussions, etc.



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ISC'15 Workshop: "The Road to Application Performance on Intel Xeon Phi Processor”

July 16, 2015

The Workshop features an overview of Intel Xeon Phi, approaches for coding for the future, real code case studies on vectorization, optimization efforts that address memory bound issues, panel discussion by programmers in the community, etc.



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SC'14 Bird of Feather Session

November 19, 2014

The Birds of Feather (BoF) supports Supercomputing 2014 attendees interested in Intel Xeon Phi tuning and debugging, and IXPUG. The BoF will start with brief presentations from academia, national labs and industry representatives sharing their experiences. The emphasis of the BoF is on performance tuning and debugging on Intel Xeon Phi systems.

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2014 IXPUG US Annual Meeting

July 8-9, 2014

IXPUG meeting will focus on user experiences and the direction ahead for Intel Xeon Phi technologies. There will also be a training tutorial designed for both beginners and intermediate-level users.



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Software developer training for the Intel® Xeon Phi™ Processor

April 22, 2014

The courses contain materials and practical exercises appropriate for developers beginning their journey to parallel programming, as well as provide cutting-edge detail to HPC experts on the best practices for Intel's multicore and many-core architectures and software development tools.


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First Meeting of the Intel eXtreme Performance Users Group (2013)

July 16-17, 2013

TACC & Intel present status updates on the software stack, programming tools, etc. followed by invited lectures from early Intel Xeon Phi users, presentations on using PerfExpert and MACPO, etc. A TACC-Intel panel session to solicit community feedback on Intel Xeon Phi programming, tools, best practices and performance.


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