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IXPUG Webinar April 25, 2024 Leveraging LLMs and Differentiable Rendering for Automating Digital Twin Construction This presentation introduces an innovative approach that combines Large Language Models (LLMs) and differentiable rendering techniques to automate the construction of digital twins. In our approach, we employ LLMs to guide and optimize the placement of objects in digital twin scenarios. This is achieved by integrating LLMs with differentiable rendering, a method traditionally used for optimizing object positions in computer graphics based on image pixel loss. Our technique enhances this process by incorporating a second modality, namely Lidar data, resulting in faster convergence and improved accuracy. This fusion of sensor inputs proves invaluable, especially for applications like autonomous vehicles, where establishing the precise location of multiple actors in a scene is crucial.
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IXPUG User Group at ISC 2024 May 15, 2024 Intel eXtreme Performance Users Group organizes second PVC User Group Meeting Discuss experiences with Intel® Data Center GPU Max Series with experts from around the world. Those working with or interested in the Intel Data Center GPU Max Series (aka Ponte Vecchio - PVC) will gather to share experiences with PVC and plans for deployment in the second meeting of the user group. Lightning talks, open to all. Please fill out the brief registration form if you'd like to attend and indicate if you'd like to give a lightning talk. Open to all.
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ISC 2024 IXPUG Workshop May 16, 2024 Third workshop on Communication, I/O, and Storage at Scale on Next-Generation Platforms – Scalable Infrastructures Next-generation HPC platforms have to deal with increasing heterogeneity in their subsystems. The workshop intends to attract system architects, code developers, research scientists, system providers, and industry luminaries who are interested in learning about the interplay of next-generation hardware and software solutions for communication, I/O, and storage subsystems tied together to support HPC and data analytics at the systems level, and how to use them effectively. The workshop will provide the opportunity to assess technology roadmaps to support AI and HPC at scale, sharing users’ experiences with early-product releases and providing feedback to technology experts.
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IXPUG Workshop at HPC Asia 2024 January 25, 2024 The International Conference on HPC in Asia-Pacific Region IXPUG Workshop at HPC Asia 2024 is an open workshop on high-performance computing applications, systems, and architecture with Intel technologies. This is a half-day workshop with invited talks and contributed papers. The workshop aims to bring together software developers and technology experts to share challenges, experiences, and best-practice methods for the optimization of HPC, Machine Learning, and Data Analytics workloads. Any research aspect related to Intel HPC products is welcome to be presented in this workshop.
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IXPUG PVC User Group at SC23 November 13, 2023 Intel eXtreme Performance Users Group organizes first PVC User Group Meeting Discuss experiences with Intel® Data Center GPU Max Series with experts from around the world. Those working with or interested in the Intel Data Center GPU Max Series (aka Ponte Vecchio - PVC) will gather to share experiences with PVC and plans for deployment in the first meeting of the PVC User Group. Lightning talks, open to all. Please fill out the brief registration form if you'd like to attend, and indicate if you'd like to give a lightning talk. Open to all. |
SC23 IXPUG BoF Wednesday, November 15, 2023 Navigating Complexity: Achieving Performance Portability in the Evolving Landscape of Heterogeneous HPC Systems With increasing demand for AI in HPC, there has been an explosion in architectures, programming models, and AI frameworks. The already-daunting task of programming for heterogenous systems has become even more challenging. This BoF, organized by the IXPUG but not limited to Intel technology, will focus on portable programming across a wide variety of architectures running a diverse set of HPC, and AI workloads. This BoF will explore challenges, state-of-the-art approaches, and emergent best practices for programming across heterogeneous systems and novel architectures, identifying common principles and practices that enable development and maintenance of software across sites, architectures, and applications.
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IXPUG Annual Conference September 21-22, 2023 Intel Headquarters, Santa Clara, CA IXPUG Annual Conference 2023 is a two-day gathering of HPC and AI experts featuring keynotes, tech talks, lightning talks, site updates, and more. The event welcomes software developers, scientists, researchers, academics, systems analysts, students, and end-users who want to share with and learn from our vibrant, global community via technical discussion and networking. With the growing convergence of HPC and AI, challenges surrounding application performance and scalability will be covered across all levels, including tuning and optimization of diverse sets of applications on HPC systems.
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IXPUG Webinar August 10, 2023 Preparing for Exascale on Aurora The Aurora exascale system is currently being deployed at Argonne National Lab. The system, utilizing Intel’s new Data Center Max Series GPUs (a.k.a. PVC) and Xeon Max Series CPU with HBM, will provide a uniquely powerful platform for leading-edge HPC, AI, and data-intensive computing applications. Scientists at Argonne National Laboratory, in collaboration with the Exascale Computing Project, Intel, and several other institutions, are preparing several dozen applications and workflows to run at scale on the Aurora system.
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ISC 2023 IXPUG Workshop May 25, 2023 Second workshop on Communication, I/O, and Storage at Scale on Next-Generation Platforms – Scalable Infrastructures The workshop intends to attract system architects, code developers, research scientists, system providers, and industry luminaries who are interested in learning about the interplay of next-generation hardware and software solutions for communication, I/O, and storage subsystems tied together to support HPC and data analytics at the systems level, and how to use them effectively. The workshop will provide the opportunity to assess technology roadmaps to support AI and HPC at scale, sharing users’ experiences with early-product releases and providing feedback to technology experts. The overall goal is to make the ISC community aware of the emerging complexity and heterogeneity of upcoming communication, I/O and storage subsystems as part of next-generation system architectures and inspect how these components contribute to scalability in both AI and HPC workloads.
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IXPUG Workshop at HPC Asia 2023 February 27, 2023 The International Conference on HPC in Asia-Pacific Region IXPUG Workshop at HPC Asia 2023 is an open workshop on high-performance computing applications, systems, and architecture with Intel technologies. This is a half-day workshop with invited talks and contributed papers. The workshop aims to bring together software developers and technology experts to share challenges, experiences, and best-practice methods for the optimization of HPC, Machine Learning, and Data Analytics workloads. Any research aspect related to Intel HPC products is welcome to be presented in this workshop.
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SC22 IXPUG BoF November 15, 2022 Performance Portability in a Heterogenous World – Pipe Dream? With increasing heterogeneity in system deployments (CPUs, GPGPUs, AI accelerators, FPGAs, IPU/DPUs), HPC users face a daunting task of programming for such diverse architectures. This BoF, organized by the IXPUG, but not limited to Intel technology, will focus on sharing expertise in portable programming across a wide variety of architectures, running a diverse set of workloads. This BoF will explore current approaches and best practices for programming across heterogeneous systems and exotic architectures, with the goal of identifying a common set of principles and practices that can be leveraged to develop and maintain software across sites, architectures, and applications.
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IXPUG Annual Conference 2022 September 28-30, 2022 Hosted by Argonne National Laboratory The 2022 IXPUG Annual Conference will be hosted by Argonne National Laboratory. HPC users and enthusiasts across the globe are invited to attend and participate. Join us to share your experiences with all aspects of adopting and employing state-of-the-art technologies and practices for optimal application execution on Intel XPU platforms. Through our interactive, open forum IXPUG brings together speakers across supercomputing, including renowned industry leaders, and experts from Intel. Together we share real-world experiences, best practices, and techniques for maximizing software productivity and efficiency.
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ISC 2022 IXPUG Workshop June 02, 2022 Communication, I/O, and Storage at Scale on Next-Generation Platforms The workshop intends to attract system architects, code developers, research scientists, system providers, and industry luminaries who are interested in learning about the interplay of next-generation hardware and software solutions for communication, I/O, and storage subsystems tied together to support HPC and data analytics at the systems level, and how to use them effectively. The workshop will provide the opportunity to assess technology roadmaps to support AI and HPC at scale, sharing users’ experiences with early-product releases and providing feedback to technology experts. The overall goal is to make the ISC community aware of the emerging complexity and heterogeneity of upcoming communication, I/O and storage subsystems as part of next-generation system architectures and inspect how these components contribute to scalability in both AI and HPC workloads.
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IXPUG Webinar April 28, 2022 Intel Fortran Compilers: A Tradition of Trusted Application Performance The Intel® Fortran Compiler is built on a long history of generating optimized code that supports industry standards while taking advantage of built-in technology for Intel® Xeon® Scalable processors and Intel® Core™ processors. Staying aligned with Intel's evolving and diverse architectures, the compiler now supports GPUs. This presentation will cover the compiler standards and path forward.
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IXPUG Webinar March 10, 2022 DAOS: Storage Innovations Driven by Intel® Optane™ Persistent Memory This presentation will provide a technical overview of Distributed Asynchronous Object Store (DAOS), a software-defined object store designed from the ground up for massively distributed Non-Volatile Memory (NVM), including Intel® Optane™ DC persistent memory and Intel Optane DC SSDs. This presentation will also introduce the performance and explain main features of DAOS.
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IXPUG Workshop at HPC Asia 2022 January 14, 2022 Fully Online Conference This is a half-day, open workshop on high performance computing applications, systems, and architecture with Intel technologies. The workshop aims to bring together software developers and technology experts to share challenges, experiences, and best-practice methods for the optimization of HPC, Machine Learning, and Data Analytics workloads on Intel® Xeon® Scalable processors and any related hardware/software platforms. The workshop will cover application performance and scalability challenges at all levels—from intra-node performance up to large-scale compute systems.
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IXPUG Webinar December 9, 2021 Multi-GPU Programming—Scale-Up and Scale-Out Made Easy, Using the Intel® MPI Library For shared memory programming of GPGPU systems, users either have to manually run their domain decomposition along available GPUs as well as GPU Tiles. Or leverage implicit scaling mechanisms that transparently scale their offload code across multiple GPU-Tiles. The former approach can be cumbersome, and the latter approach is not always the best performing one. The Intel MPI library can take that burden from users by enabling the user to program only for a single GPU / Tile and leave the distribution to the library. This can make HPC / GPU programming much easier. Therefore, Intel® MPI does not just allow to pin individual MPI ranks to individual GPUs or Tiles, but also allows users to pass GPU memory pointers to the library.
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IXPUG BoF at SC21 November 17, 2021 Best Practices for Benchmarking Diverse Architectures with Varied Workloads This BoF, organized by the Intel eXtreme Performance Computing Users Group, will focus on sharing expertise in benchmarking computing systems across a variety of homogeneous and heterogeneous architectures with a variety of workloads. With increasing heterogeneity, the accurate and adequate comparison of performance across architectures and applications has become a growing challenge. This BoF will explore current approaches and best practices for benchmarking heterogeneous systems and exotic architectures, with the goal of identifying a unified set of principles and practices that can be leveraged to produce benchmarking results that are appropriate for direct comparison across sites, architectures, and applications. |
oneAPI Developer Summit at SC November 14, 2021 Global Experts on eXtreme Performance Panel The Intel eXtreme Performance Users Group (IXPUG) will present a brief overview of the organization and its activities, followed by a panel discussion focused on the expected adoption, support and application of oneAPI at various computing sites around the world. Experts from the various sites will discuss ongoing work with oneAPI and plans for its support and application at their site, in addition to elucidating on the expected impact on their user community. The session will close with a brief overview of opportunities for involvement in upcoming IXPUG activities. |
IXPUG Annual Conference 2021 October 19-21, 2021 Virtual Organized by TACC This IXPUG conference is focused on all aspects of adopting and employing state-of-the-art technologies and practices for optimal application execution on Intel XPU platforms. Key themes: high-performance computing, data analytics, artificial intelligence (machine learning and deep learning), HPC in the cloud, and COVID-19 related biomedical simulations and data analytics applications. |
IXPUG Webinar August 12, 2021 IMPECCABLE: A Dream Pipeline for High-Throughput Virtual Screening, or a Pipe Dream? In silico methodologies need to be improved to better select lead compounds that can proceed to later stages of the drug discovery protocol accelerating the entire process. No single methodological approach can achieve the necessary accuracy with required efficiency. Here we describe multiple methodological and supporting infrastructural innovations at scale. Specifically, how we used TACC’s Frontera on > 8000 compute nodes to sustain 144M/hour docking hits, and to screen ∼100 Billion drug candidates. |
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IXPUG Mid-Year Workshop 2021 June 21, 2021 Virtual Organized by TACC IXPUG continues to see heterogeneous HPC architectures (XPUs) become a dominating supercomputing platform for state-of-the-art model-driven simulations and artificial intelligence and big data applications to help society cope with significant challenges. COVID-19 posed a grand challenge to the entire world. This workshop is organized along with two major themes both at the technical and at the societal level – (i) experiences with oneAPI on GPUs and (ii) COVID-19 related biomedical simulations and data analytics applications. |
IXPUG Webinar April 22, 2021 Visual Analysis on TACC Frontera using the Intel oneAPI Rendering Toolkit TACC Frontera handles the largest simulation runs for open-science researchers supported by the National Science Foundation. Due to the data sizes involved, the scientific analysis is most easily performed on Frontera itself, often done “in situ” without writing the full data to disk. This talk will present recent work on Frontera that uses the Intel oneAPI Rendering Toolkit to perform both batch and interactive visual analysis across a range of scientific domains. |
IXPUG Webinar March 11, 2021 Performance Optimizations for End-to-End AI Pipelines The trifecta of high volumes of data, abundant compute availability on cloud and on-premise, and rapid algorithmic innovations enable data scientists and AI researchers to do fast experiments, prototyping, and model development at an accelerated pace that was never possible before. In this talk, we will touch upon a variety of software packages, libraries, and tools that can also help HPC practitioners push the envelope of applying AI in their application domains and simulations at-scale. We will cover examples and talk about how to create efficient end-to-end AI pipelines with large data sets in-memory, security, and other features through Intel-optimized software packages such as Intel® Distribution of Python, Intel® Optimized Modin, Intel® Optimized Sklearn, and XGBoost, as well as DL Frameworks such as Intel® Optimized Tensorflow and Intel® Optimized PyTorch tuned and enabled with new hardware features and instructions every new CPU generation. |
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IXPUG Webinar February 18, 2021 Migrating from CUDA-only to Multi-Platform DPC++ We will demonstrate how an existing CUDA stencil application code can be migrated to DPC++ with the help of the Compatibility Tool. Highlights the crucial differences between the two programming environments in the context of migrating the tsunami simulation easyWave. Discussion includes steps for making the code to compliant with the SYCL standard. We will also show that the migrated code can run on a wide range of platforms starting from CPUs, over GPUs, to FPGAs. |
IXPUG Workshop at HPC Asia 2021 January 22, 2021 Jeju, South Korea (Online Conference) This is a half-day, open workshop on high performance computing applications, systems, and architecture with Intel technologies. The workshop aims to bring together software developers and technology experts to share challenges, experiences, and best-practice methods for the optimization of HPC, Machine Learning, and Data Analytics workloads on Intel® Xeon® Scalable processors, Intel® Xeon Phi™ processors, Intel® FPGA, and any related hardware/software platforms. |
IXPUG at SC 2020 Virtual November 19, 2020 Accelerating Code Development with Intel oneAPI on Intel XPUs The session highlights community activities to prepare for the use of Intel XPUs (GPUs, FPGAs) in large systems; e.g, oneAPI for Aurora and the science driving the work. Programming for heterogeneous platforms containing XPUs using the Intel oneAPI programming framework is the central topic. This builds on IXPUG community work in preparing codes for the parallelism of Intel CPUs and Xe hardware. Experts from Zuse Institute Berlin, Argonne National Laboratory, and Intel Corporation share plans, priorities and early experiences with oneAPI. |
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IXPUG Annual Fall Conference Virtual October 13-16, 2020 Organized by TACC This Intel eXtreme Performance User Group (IXPUG) conference is focused on all aspects of adopting and employing state-of-the-art technologies and practices for optimal application execution. This includes accelerators (e.g., co-processors, FPGAs, GPUs), as well as topics related to system hardware beyond the processor (memory, interconnects, etc.), software tools, programming models, HPC workloads, troubleshooting, and more — all with a focus on Intel platforms. |
IXPUG Webinar July 1, 2020 Migrating Your Existing CUDA Code to DPC++ Best practices for using a one-time migration tool that migrates CUDA applications into standards-based Data Parallel C++ (DPC++) code. Topics include: An overview of the DPC++ language, including why it was created and how it benefits developers An overview of the Intel DPC++ Compatibility Tool itself—what it is and what it does Real-world examples of the code-migration concept, including the process and expectations |
IXPUG Webinar February 20, 2020 Performance Optimization of Intel® oneAPI Applications Maximizing performance takes a mix of scalar, vector, matrix, and spatial (SVMS) architectures deployed in CPU, GPU, FPGA, and other future accelerators. Intel® oneAPI products will deliver the tools needed to deploy applications and solutions across SVMS architectures. Kevin O’Leary of Intel’s software tools group will show the oneAPI features that focus on performance optimization, including the analysis tools Intel® VTune™ Profiler(Beta) and Intel® Advisor(Beta). |
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IXPUG Workshop at HPC Asia 2020 January 17, 2020 Fukuoka, Japan Agenda announced! Half-day, open workshop on high performance computing applications, systems, and architecture with Intel technologies. The workshop aims to bring together software developers and technology experts to share challenges, experiences and best-practice methods for the optimization of HPC, Machine Learning, and Data Analytics workloads on Intel® Xeon® Scalable processors, Intel® Xeon Phi™ processors, Intel® FPGA, and any related hardware/software platforms. |
IXPUG BoF at SC19 November 20, 2019 Denver, Colorado This SC19 Birds of a Feather will focus on achieving performance at scale on current and future large Intel-based systems. With the recent announcement of a planned 2021 exascale system that includes Intel GPUs, IXPUG’s optimization targets will be expanding to include the full line of Intel processors, including FPGAs. Join like-minded researchers, tool developers, application programmers, HPC center staff, and industry experts to share tips and techniques gained through deployments on large-scale systems and look to the future. |
IXPUG Webinar November 14, 2019 Speeding up Genomic Sequencing Analysis with Intel® Optane™ DC Persistent Memory Technology Prof. Knut Reinert of Freie Universität Berlin will describe the results of his new “binning directory” data structure for genomic database searching, its performance relative to existing disk-based solutions, and its potential to accelerate innovation in health and life science. |
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IXPUG Webinar October 10, 2019 Optimize for Both Memory and Compute on Modern Hardware Using Roofline Model Automation in Intel ® Advisor Software must be optimized for both Compute (including SIMD vector parallelism) and effective memory sub-system utilization to achieve scaled performance on modern hardware. In this talk we present state-of-the-art Intel Advisor Roofline performance model automation which helps to identify memory bottlenecks and balance between CPU and memory utilization. |
IXPUG Annual Conference 2019 September 24–27, 2019 Globe of Science and Innovation at CERN (Geneva, Switzerland) Join Intel and other industry experts at 4-day, interactive, open forum This IXPUG conference is focused on all aspects of adopting and employing state-of-the-art data-processing technologies and techniques for optimal application execution. This includes accelerators (e.g. FPGAs, GPUs), as well as topics related to system hardware beyond the processor (memory, interconnect, etc.), software tools, programming models, new workloads, and more — all with a focus on Intel platforms. (Photo courtesy of CERN) |
IXPUG Webinar September 12, 2019 Accelerate Your Inferencing with Intel® Deep Learning Boost Learn about Intel® Deep Learning Boost (Intel® DL Boost), and its Vector Neural Network Instructions (VNNI). These are a new set of Intel® Advanced Vector Extension 512 (Intel® AVX-512) instructions that are designed to deliver significantly more efficient Deep Learning inference acceleration. |
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IXPUG Webinar July 11, 2019 Scaling Distributed TensorFlow Training with Intel’s nGraph Library on Xeon® Processor Based HPC Infrastructure In this talk, we will present the details on the bridge that connects TensorFlow to nGraph for a Xeon CPU backend. We will demonstrate state-of-the-art (SOTA) accuracy and convergence for ResNet-50 against ImageNet-1K on multiple Xeon Skylake nodes. Show More
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ISC19 IXPUG Workshop June 20, 2019 Frankfurt, Germany (Marriott, room Megabyte) Using FPGAs to Accelerate HPC & Data Analytics on Intel-Based Systems ISC19 IXPUG Workshop brings together software developers, scientist, academia, industry luminaries to share learnings around the integration and use of FPGA devices in HPC, Data Analytics, and Artificial Intelligence (Machine and Deep Learning) workloads in Intel-based HPC systems.
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IXPUG In Situ Analysis Hackathon May 28–30, 2019 Santa Fe, NM Collaborate with experts from TACC, LANL, Kitware, Intelligent Light, and Intel for three days in Santa Fe!
Simulation processing capability continues to outpace disk I/O capacity, making it increasingly intractable and impractical to save checkpoints or large results files for later analysis. This issue is particularly acute for Extreme Performance users, as modern Intel processors offer a high degree of parallelism and a large memory space per node, which increases both the time and opportunity cost of saving to disk.
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IXPUG Webinar May 09, 2019 Deeply-Pipelined FPGA Clusters Make DNN Training Scalable This talk will introduce a framework, FPDeep, which uses a hybrid of model and layer parallelism to configure distributed reconfigurable cluster to train DNNs. This leads to high parallelism and utilization and also minimizes the time features need to be cached while waiting for back-propagation.
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IXPUG Webinar April 11, 2019 A Study of SIMD Vectorization for Matrix-Free Finite Element Method This talk will present study on the cross-element vectorization in the finite framework Firedrake and demonstrate the efficacy of such an approach by evaluating a wide range of matrix-free operators spanning different polynomial degrees and discretizations on two recent INTEL CPUs using three mainstream compilers.
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IXPUG Webinar March 14, 2019 Scalable and Flexible Distributed with OSPRay's Distributed API and FrameBuffer This talk will present work on an asynchronous image processing and compositing framework for multi-node rendering in OSPRay, dubbed the Distributed FrameBuffer. The talk demonstrates that this approach achieves performance superior to the state of the art for common use cases, while providing the flexibility to support a wide range of parallel rendering algorithms and data distributions. By building on this framework, extended OSPRay with a data-distributed API, enabling its use in data-distributed and in situ visualization applications.
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IXPUG Webinar February 14, 2019 Evaluation of Intel Memory Drive Technology Performace for Scientific Applications This talk will present benchmark data for IMDT, which is a new generation of Software-defined Memory(SDM) based on Intel ScaleMP collaboration and using 3D XPoint based Intel SSD called Optane. IMDT performance was studied using synthetic benchmarks, scientific kernels, and applications. |
IXPUG Workshop at HPC Asia Conference January 14, 201913:30-17:00, BallRoom C Guang Zhou, China IXPUG Workshop Asia 2019 is an open workshop on high performance computing application, system and architectural with Intel technologies. This is half day workshop aims to bring together software developers and technology experts to share challenges, experience and best-practice methods for optimization of HPC, Machine Learning and Data Analytic workloads on Intel Xeon Phi and Xeon Scalable. |
IXPUG Webinar January 10, 2019 Massively Scalable Computing Method for Handling Large Eigenvalue Problem for Nanoelectronics Modeling This talk will help you learn how Lanczos iterative algorithm can be extended with a parapple computing to solve highly degenerated systems. The talk will address the performance benefits of the core numerical operations in Lanczos iteration, which can be driven with manycore processors (KNL) compared to the heterogeneous systems containing PCI-E and-in devices.
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IXPUG BoF at SC18 November 15, 2018 Achieving Performance on Large-Scale Intel Xeon-Based System This BoF,organized by Intel Extreme Computing Users Group(IXPUG), will focus on achieving performance at scale on large Xeon-based systems. The community has gained experience in deloying generation of Xeon Phi and more recently the Xeon Scalable family of processors and is moving to achieve sustained performance. |
IXPUG Working Groups October 11, 2018 Intel Optane Solution in HPC This session focused on the latest Intel Optane technolohies and the way it's used by HPC customers. Attendees will learn about the best usage models and benefits Intel Optane introduces for fast storage or extending system memory.
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IXPUG Annual Fall Conference Co-Organized by Sandia National Laboratories & Los Alamos National Laboratory September 25-28, 2018 Oregon, US The Intel eXtreme Performance Users Group (IXPUG) is an active community led forum for sharing industry best practices, techniques, tools, etc. for maximizing efficiency on Intel platforms and products. This meeting will focus on all aspects of employing, adopting many-core processing technologies and techniques for optimal application execution. |
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IXPUG Working Groups August 9, 2018 Machine Learning at Scale Deep Learning has revolutionized the fields of computer vision, speech recognition, robotics and control systems. At NERSC, we have applied deep learning to problems in cosmology and climate science, focusing on areas that require supercomputing resources to solve real scientific challenges.
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IXPUG Software-Defined Visualization Workshop Hosted by Argonne National Laboratory Jul 10-12, 2018 This three-day event is aimed at simulation developers and domain experts with simulation implementation expertise. After an initial orientation to in-situ capabilities, the workshop will combine domain expert attendees with visualization experts from TACC, Kitware, Intelligent Light and Intel to design and implement a proof-of-concept in-situ visualization for each attendee's simulation. The workshop will provide a functional prototype on which to continue in-situ development, as well as identifying barriers to in-situ analysis for particular scientific domains. |
IXPUG Workshop at ISC June 28, 2018 " Many-core Computing on Intel Processors: Applications, Performance and Best-Practice Solutions" This one full-day IXPUG workshop will bring together software developers and technology experts to share challenges, experiences and best-practice methods ,for the optimization of HPC, Machine Learning (ML) and Data Analytics (DA) workloads on Intel Xeon Scalable Processors and Intel Xeon Phi Processors. |
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IXPUG Working Groups Jun 14, 2018 Using Roofline Analysis to Analyze, Optimize, & Vectorize Iso3DFD with Intel® Advisor This presentation will introduce the use of Intel® Advisor to help you enabling vectorization in your application. We will use the Roofline Model in Intel Advisor to see the impact of our optimizations. We will also demonstrate how Intel Advisor can detect wrong memory access patterns or loop carried dependency in your application. The case study we will use is Iso3DFD. |
IXPUG Working Groups May 10, 2018 High Productivity Languages This session addresses challenges of numerical analysis and simulations at scale through tools, such as Python, which are often used for prototyping are not designed to scale to large problems. Covering a brief overview of scalability aspects with respect to modern hardware architecture we will characterize what the problem at scale is, its inherit characteristics and how these map onto software design choices.
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April 22-25, 2018 Thuwal, Saudi Arabia This meeting is hosted by King Abdullah University of Science and Technology (KAUST) the IXPUG Conference will focus on the areas of energy, climate simulations and analytics based on PDE’s or analytics based on geospacial statistics are limited to memory, processing or both. This is the first IXPUG meeting in the Middle East.
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IXPUG Working Groups April 12, 2018 Topology and Cache Coherence in Knights Landing and Skylake Xeon Processors Intel's second-generation Xeon Phi (Knights Landing) and Xeon Scalable Processor ("Skylake Xeon") are both based on a new 2-D mesh architecture with significant changes to the cache coherence protocol. This talk will review some of the most important new features of the coherence protocol (such as "snoop filters", "memory directories", and non-inclusive L3 caches) from a performance analysis perspective.
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IXPUG Working Groups March 8, 2018 Compiler Prefetching for Knights Landing We will cover some of the recent changes in the compiler-based prefetching (for Knights Landing and Skylake) and provide tips on how to tune for performance using compiler prefetching options, pragmas and prefetch intrinsics. |
IXPUG Annual Spring Conference Hosted by CINECA March 5-7, 2018 Bologna, Italy The Intel eXtreme Performance Users Group (IXPUG) is an active community led forum for sharing industry best practices, techniques, tools, etc. for maximizing efficiency on Intel platforms and products. This meeting will focus on all aspects of employing and adopting manycore processing technologies and techniques for optimal application execution.
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IXPUG Working Groups February 8, 2018 Threading Building Blocks (TBB) Flow Graph: Expressing and Analyzing Dependencies in Your C++ Application Developing for heterogeneous systems is challenging because applications may be composed of many layers of parallelism and employ a diverse set of programming models or libraries. This session focuses on Flow Graph, an extension to the Threading Building Blocks (TBB) interface that can be used as a coordination layer for heterogeneity that retains optimization opportunities and composes with existing models. Finally, we validate this approach by presenting use cases of applications using Flow Graph..
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IXPUG Workshop at HPC Asia Conference January 28-31, 2018 Tokyo, Japan The Intel eXtreme Performance Users Group (IXPUG) is an active community led forum for sharing industry best practices, techniques, tools, etc. for maximizing efficiency on Intel platforms and products. This is a half day workshop with contributed papers and key note talks. Any research aspect related to Intel Xeon Phi is welcome to present to share this advanced technology for high performance computing.
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IXPUG Working Groups January 11, 2018 Vectorization of Inclusive/Exclusive Scan in Compiler 19.0 |
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November 14, 2017 IXPUG Birds-of-a-Feather (BOF) Session, Denver Convention Center, Room 603 Usability, Scalability and Productivity on Many-Core Processors: Intel Xeon Phi and Beyond |
Intel® HPC Developer Conference 2017The Intel® HPC Developer Conference 2017 features industry luminaries sharing best practices and techniques to help realize the potential of these technologies. Attendees will gain hands-on experience with Intel platforms, network with peers and industry experts, and gain insight on recent technology advances to maximize software efficiency that help drive discovery. IXPUG is a sponsor of this event.
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2017 IXPUG US Annual Meeting September 26-28, 2017 The IXPUG US-based Annual Meeting this year is hosted by the Texas Advanced Computing Center (TACC) in Austin, TX. This meeting will focus on all aspects of employing and adopting manycore processing (KNL/KNC) technologies and techniques for optimal application execution. Presentations, keynotes, a panel discussion, and a roadmap will provide details on discoveries, experiences, methods, and the future for efficient and scalable manycore computing. There will also be hands-on KNL training tutorials, designed for both beginners and intermediate-level users.
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IXPUG Workshop: "Experiences on Intel Knights Landing at the One Year Mark" June 22, 2017 This one full-day IXPUG workshop at ISC 2017 is about sharing ideas, implementations, and experiences that will help users take advantage of new Intel Xeon Phi features, such as AVX512 and high-bandwidth MCDRAM memory, as well as relevant high-performance system fabrics on large-scale KNL-based systems (e.g. OmniPath).
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IXPUG "Birds of a Feather" (BOF) at ISC: Achieving Performance on Large-Scale Intel Xeon Phi Knights Landing Systems June 19, 2017 This BOF, conducted by leaders of the 500+ member Intel eXtreme Performance Users Group (IXPUG), seeks to build and strengthen a community among those developing HPC applications for large-scale systems incorporating Intel Xeon Phi processors and co-processors.
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IXPUG Russia Annual Meeting June 1-2 Hosted by the Joint Supercomputer Center of the Russian Academy of Sciences, Moscow Intel annually holds an International conference IXPUG Russia (Intel eXtreme Performance Users Group). We will hold the event to share experience in practical issues of development and debugging multi-threaded applications on multi-core processors Intel® Xeon Phi™. The focus of this year will be dedicated to the user experience on Intel® Xeon Phi™ 2nd generation (Knights Landing).
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IXPUG Software-Defined Visualization Workshop Hosted by the Texas Advanced Computing Center May 22-25, 2017 This four-day event is aimed at simulation developers and domain experts with simulation implementation expertise. After an initial orientation to in-situ capabilities, the workshop will combine domain expert attendees with visualization experts from TACC, Kitware, and Intel to design and implement a proof-of-concept in-situ visualization for each attendee's simulation. The workshop will provide a functional prototype on which to continue in-situ development, as well as identifying barriers to in-situ analysis for particular scientific domains.
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IXPUG Annual Spring Meeting Hosted by the University of Cambridge, UK April 10-13, 2017 Hosted by the The Stephen Hawking Centre for Theoretical Cosmology (CTC) at the University of Cambridge, the IXPUG Annual Spring Conference 2017 will feature presentations and tutorials. Application performance and scalability challenges at all levels will be covered, including application tuning on large KNL systems. |
SC’16 Bird of Feather (BoF): “Optimizing Performance on Intel® Xeon Phi and Beyond: Unleashing the Power of Many-Core Processors”November 16, 2016 12:15pm, Room 355-F This IXPUG BoF will provide a forum for application and tool developers, HPC center staff, and Intel experts to discuss their early successes and challenges. This BOF will showcase successes in modernizing code for KNL and beyond, highlighting tuning methodologies, tools features, and real-world impact and community codes. IXPUG is an independent users group for anyone interested in application performance on the Intel Xeon Phi.
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Intel® HPC Developer Conference November 12-13, 2016, Sheraton Salt Lake City Hotel Join high performance computing (HPC) experts at the 2016 Intel® HPC Developer Conference, November 12-13 in Salt Lake City! This free event brings together architecture experts and developers to discuss, share and highlight the latest in supercomputing. Get technical and hands-on knowledge, learn from real world examples, and gain insights about future technologies from industry leaders. Register Today!
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2016 IXPUG US Annual MeetingSeptember 19-22, 2016 This IXPUG US-based annual meeting is a combination of tutorials, workshops, and plenary presentations featuring case studies around optimization work on open source codes by various community experts. This event will be hosted by Argonne National Laboratory in Lemont, Illinois.
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ISC’16 Workshop: “Application Performance on Intel Xeon Phi – Being Prepared for Knights Landing and Beyond” June 23, 2016 The workshop brought together software developers and technology experts to share challenges, experiences and best-practice methods for the optimization of HPC workloads on the Intel Xeon Phi. The workshop will cover application performance and scalability challenges at all levels - from single processor, to moderately-scaled cluster, up to large HPC configurations with many Xeon Phi devices. |
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ISC’16 Birds of Feather (BoF): “Gearing Up Application Performance for Intel Xeon Phi (KNL) Supercomputers” June 22, 2016 The IXPUG BoF event showcased a Knights Landing demo, featuring the Intel Xeon Phi™ Processor based Ninja Developer Platform hardware. Community led presentations on cases studies from the IXPUG Monthly Working Groups, Lightning Talks, Tools Talks and discussions to present performance for selected benchmarking cases. |
TACC Knights Landing Tutorial June 18, 2016 Texas Advanced Computing Center (TACC) partnered with Intel Corp. to offer a tutorial to Intel Xeon Phi program developers. The training provided hands-on exercises that were executed on the Stampede Knights Landing system at TACC. |
2016 IXPUG Russia Annual MeetingJune 9-10, 2016 The IXPUG Russia event was hosted by Saint-Petersburg Polytechnic University. This workshop and tutorial sessions addressed key applications from the end user and developers’ perspective, case studies, roundtable discussions. Attendance from Russia community experts, sharing learnings with the broader HPC developers and includes an academic teaching session.
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2016 IXPUG Europe Annual MeetingMarch 14-18, 2016 This event was a combination of a workshop, tutorial and community networking and shared learnings, etc. Host by IT4Innovations National Supercomputing Centre. Included workshops, tutorials and code dungeon address a wide range of optimization technics, teaching materials, etc.
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SC15 Birds of a FeatherNovember 18, 2015 This Birds of a Feather supported SC15 in giving attendees insight into how we are paving the way for Performance on Intel® Knights Landing Processors and beyond: Unleashing the Power of Next-Generation Many-Core Processors. We had approximately 180 participants.
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2015 IXPUG US Annual MeetingSeptember 28-October 2, 2015 The IXPUG annual meeting is a forum where the broader community of Intel Xeon Phi users can share best practices, optimization approaches and results. There were hands-on tutorials, keynote and general presentations, optimization workshops, libraries and program models, deep dive code dungeon showcasing real time case study project work.
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ISC'15 Bird of Feather: "Unleashing the Power of Next-Generation Many-Core Processors”July 15, 2015 The Birds of Father (BoF) covers insight to Intel Xeon Phi (Knights Landing) architecture, monthly public optimization forums, leveraging Intel Software tools, Lightning Talks from the broader community, various Tool Talk Discussions, etc.
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ISC'15 Workshop: "The Road to Application Performance on Intel Xeon Phi Processor”July 16, 2015 The Workshop features an overview of Intel Xeon Phi, approaches for coding for the future, real code case studies on vectorization, optimization efforts that address memory bound issues, panel discussion by programmers in the community, etc.
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SC'14 Bird of Feather SessionNovember 19, 2014 The Birds of Feather (BoF) supports Supercomputing 2014 attendees interested in Intel Xeon Phi tuning and debugging, and IXPUG. The BoF will start with brief presentations from academia, national labs and industry representatives sharing their experiences. The emphasis of the BoF is on performance tuning and debugging on Intel Xeon Phi systems. |
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2014 IXPUG US Annual MeetingJuly 8-9, 2014 IXPUG meeting will focus on user experiences and the direction ahead for Intel Xeon Phi technologies. There will also be a training tutorial designed for both beginners and intermediate-level users.
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Software developer training for the Intel® Xeon Phi™ ProcessorApril 22, 2014 The courses contain materials and practical exercises appropriate for developers beginning their journey to parallel programming, as well as provide cutting-edge detail to HPC experts on the best practices for Intel's multicore and many-core architectures and software development tools.
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First Meeting of the Intel eXtreme Performance Users Group (2013)July 16-17, 2013 TACC & Intel present status updates on the software stack, programming tools, etc. followed by invited lectures from early Intel Xeon Phi users, presentations on using PerfExpert and MACPO, etc. A TACC-Intel panel session to solicit community feedback on Intel Xeon Phi programming, tools, best practices and performance.
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