Fifth workshop on Communication, I/O, and Storage at Scale on Next-Generation Platforms – Scalable Infrastructures

ISC 2025 IXPUG Workshop

Call for Submissions: https://easychair.org/cfp/ISC-2025-IXPUG-Workshop

Workshop Date: Friday, June 13, 2025 9:00 AM to 6:00 PM · 9 hr. (Europe/Berlin)

Location: Hall X2 - 1st floor, in-person at ISC 2025, Hamburg, Germany

Registration: To attend the IXPUG Workshop, you must register for the ISC 2025 Workshop Pass: https://isc-hpc.com/attendance/registration/

Event Description:
Next-generation HPC platforms have to deal with increasing heterogeneity in their subsystems. These subsystems include internal high-speed fabrics for inter-node communication; storage system integrated with programmable data processing units (DPUs) and infrastructure processing units (IPUs) to support software-defined networks; traditional storage infrastructures with global parallel POSIX-based filesystems complemented with scalable object stores; and heterogeneous compute nodes configured with a diverse spectrum of CPUs and accelerators (e.g., GPU, FPGA, AI processors) having complex intra-node communication.

The workshop intends to attract system architects, code developers, research scientists, system providers, and industry luminaries who are interested in learning about the interplay of next-generation hardware and software solutions for communication, I/O, and storage subsystems tied together to support HPC and data analytics at the systems level, and how to use them effectively. The workshop will provide the opportunity to assess technology roadmaps to support AI and HPC at scale, sharing users’ experiences with early-product releases and providing feedback to technology experts. The overall goal is to make the ISC community aware of the emerging complexity and heterogeneity of upcoming communication, I/O, and storage subsystems as part of next-generation system architectures and inspect how these components contribute to scalability in both AI and HPC workloads.

Agenda
(All times are shown in CEST / Hamburg Time, UTC+2)

Session 1: Chair: Steffen Christgau, Zuse Institute Berlin

09:00 - 09:05 Welcome Note by David Martin, Vice-President of IXPUG (Argonne National Laboratory) – IXPUG

09:05 - 09:45 Keynote Talk: GigaScale FluidX3D CFD simulations from communication and IO perspective [Slides]
Speaker: Dr. Moritz Lehmann, Intel

09:45 - 10:10 Invited Talk: Algorithms and Applications that can leverage DPUs [Slides]
Speaker: Jeff Young, Georgia Institute of Technology

10:10 - 10:35 Invited Talk: ODOS: OpenMP offload for DPUs [Slides]
Speaker: Sergio Iserte, Barcelona Supercomputing Center

10:35 - 11:05 Invited Talk: BF-3 and Data Path Accelerator (DPA) [Slides]
Speaker: Rich Graham, NVIDIA

11:05 - 11:30 Coffee Break

11:30 - 12:00 Paper: MOSE: Introducing a Unified Framework to Assess Applications Benefit from Offloading MPI Communications, [Slides]
Speaker: Michele Esposito Marzino, Barcelona Supercomputing Center (BSC)

12:00 - 12:30 Paper: DOCA UROM: A Vehicle for Offloading HPC and AI to DPUs [Slides]
Speaker : Rohit Zambre, NVIDIA

12:30 - 1:00 Invited Talk : Demystifying BlueField DPUs: Architectural Insights and Acceleration of Compression Workloads [Slides]
Speaker : Dr. Xiaoyi Lu, Associate Professor of Computer Science and Engineering at UC Merced

01:00-2:00 Lunch Break

Session 2: Chair: Oscar Hernandez Mendoza, ORNL

02:00 - 02:30 KeynoteTalk: Network and IO Optimizations for AI and HPC applications at scale on Aurora. [Slides]
Speakers : Huda Ibeid & Premanand Sakarda, Intel

02:30 - 03:00 Paper: Accelerating I/O in Scientific Workflows with the Impact of Apache Ignite’s In-Memory File System [Slides]
Presenter : Vijayalakshmi Saravanan, The University of Texas at Tyler

03:00 - 03:30 Paper: Combining Malleability and Distributed Control Mechanisms to Reduce I/O Contention [Slides]
Speaker: David E. Singh, Universidad Carlos III de Madrid

03:30 - 04:00 Invited Talk Invited Talk : SmartNIC with composable disaggregated infrastructure (CDI) work [Slides]
Speaker: Ryan Eric Grant, Queen's University

4:00 - 4:05 Workshop Closing Remarks
David Martin (Argonne Leadership Computing Facility, Argonne National Laboratory)

Workshop Format:
The workshop will have a keynote, full (30 min) talks and lightning talks (10-15 min). While in-person presentations are preferred, pre-recorded videos will be allowed as presentations in exceptional cases.

Call for Submissions:
The submission process will close on March 7, 2025, AoE. All submitters should provide content that represents an Extended Abstract, max. 6-12 pages in LNCS format via the IXPUG EasyChair: https://easychair.org/cfp/ISC-2025-IXPUG-Workshop. Notifications will be sent to submitters by April 2, 2025, AoE. The page limit is 12 pages for each paper, which includes a bibliography and appendices, with two possible extra pages after the review to address the reviewer’s comments. The page limit includes bibliography and appendices.

Topics of Interest are (but not limited to):

Holistic view on performance of next-generation platforms (with emphasis on communication, I/O, and storage at scale)
Application-driven performance analysis with various HPC fabrics
Software-defined networks in HPC environments
Experiences with emerging scalable storage concepts, e.g., object stores using next-generation HPC fabrics
Performance tuning on heterogeneous platforms from multiple vendors including impact of I/O and storage
Performance and portability using network programmable devices (DPU, IPU)
Best practice solutions for application programming with complex communication, I/O, and storage at scale

Keywords:
high-performance fabrics, data and infrastructure processing units, scalable object stores as HPC storage subsystems, heterogeneous data processing, holistic system view on scalable HPC infrastructures

Review Process:
All submissions within the scope of the workshop will be peer-reviewed and will need to demonstrate the high quality of the results, originality and new insights, technical strength, and correctness. We apply a standard single-blind review process, i.e., the authors will be known to reviewers. The assignment of reviewers from the Program Committee will avoid conflicts of interest.

Important Dates:

Deadline for submissions: Friday, March 7, 2025
Final acceptance notification: Wednesday, April 2, 2025
Camera-ready submission deadline (Workshop Papers): Friday, May 16, 2025
Camera-ready presentation: Friday, June 6, 2025
Workshop day: Friday, June 13, 2025, 9:00 a.m. – 6:00 p.m.

Organizers:

David Martin, Argonne Leadership Computing Facility, Argonne National Laboratory
Steffen Christgau, Zuse Institute Berlin
Amit Ruhela, Texas Advanced Computing Center (TACC), The University of Texas at Austin
John Pennycook, Intel Corporation
R. Glenn Brook, Cornelis Networks
Clayton Hughes, Sandia National Laboratories
Oscar R. Hernandez Mendoza, Oak Ridge National Laboratory

Program Committee:

R. Glenn Brook, Cornelis Networks
Toshihiro Hanawa, The University of Tokyo
Clayton Hughes, Sandia National Laboratories
Nalini Kumar, Intel Corporation
James Lin, Shanghai Jiao Tong University
Hatem Ltaief, King Abdullah University of Science & Technology
David Martin, Argonne Leadership Computing Facility, Argonne National Laboratory
Christopher Mauney, Los Alamos National Laboratory
Oscar R. Hernandez Mendoza, Oak Ridge National Laboratory
John Pennycook, Intel Corporation
Amit Ruhela, Texas Advanced Computing Center (TACC), The University of Texas at Austin

Contact:

Please contact This email address is being protected from spambots. You need JavaScript enabled to view it. with any general questions.