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IXPUG Workshop: Many-core Computing on Intel Processors: Applications, Performance and Best-Practice Solutions


Location: Marriott Hotel - Matrix Room (5th floor), Frankfurt, Germany

Date: Thursday, June 28, 2018, 9:00am-6:00pm

Registration: The workshop is held in conjunction with the ISC 2018 in Frankfurt (Main). To attend the IXPUG workshop, you have to register for ISC Workshops. More information is on the ISC 2018 conference website.

Event Description: The workshop will bring together software developers and technology experts to share challenges, experiences and best‐practice methods for the optimization of HPC, Machine Learning (ML) and Data Analytics (DA) workloads on Intel Xeon Scalable Processors and Intel Xeon Phi Processors. The workshop will cover application performance and scalability challenges at all levels – from intra-node performance up to large-scale compute systems.

The keynote will introduce the main features of current-generation Intel processors models for HPC and ML/DA workloads - including the various memory configurations and modes of operation available - and provide a refresher on what’s public about future processor generations.

The submitted talks cover optimization and scalability topics in real-world HPC and ML applications, e.g. data layouts and code restructuring for efficient SIMD operation, utilization of new AVX-512 instructions, work distribution and thread management. Furthermore, aspects related to deeper memory hierarchies (High-Bandwidth Memory, node-local persistent storage) are of particular interest. The usability of tools for development, debugging and performance analysis will be covered.

The panel session provides an opportunity to discuss optimization strategies for Intel many-core processors including Intel Xeon SP series, “Knights Landing” (KNL), and “Knights Mill” (KNM), and to provide feedback to the toolchain developers.


Start End Title Speaker* and Authors
09:00 09:15 IXPUG Welcome  
09:15 10:00


HPC's Impact on the Digital Economy Transformation

Mark Seager (Intel)
10:00 10:30 CSB_Coo sparse matrix vector performance on Intel Xeon and Xeon Phi architectures Brandon Cook, Charlene Yang, Thorsten Kurth and Jack Deslippe (LBL)
10:30 11:00 Lessons Learned from Optimizing Kernels for Algebraic Multigrid Solvers in Lattice QCD Balint Joo (Jefferson Lab) and Thorsten Kurth (LBL)
11:00 11:30 Break  
11:30 12:00


Mapping SIMD into Kokkos

Simon Hammond (Sandia)
12:00 12:30 Distributed Training of Generative Adversarial Network Sofia Vallecorsa (CERN), Federico Carminati (CERN), Gulrukh Khattak (CERN), Damian Podareanu (SURFSARA) ‎, Valeriu Codreanu (SURFSARA), Vikram Saletore (Intel) and Hans Pabst (Intel)
12:30 12:45 Deep Learning with Many-Core Processors and BigDL using Scientific Datasets David Ojika (Univ. Florida) and Bhavesh Patel (Dell)
12:45 13:00 Performance optimization for modern many-core architectures using PSYclone embedded-DSL Sergi Siso, Rupert Ford and Andrew Porter (STFC)
13:00 14:00 Lunch  
14:00 15:00


OpenMP API Version 5.0: A Story about Threads, Tasks, and Devices

Michael Klemm (CEO OpenMP)
15:00 15:15

Optimised Data Decomposition for Reduced Communication Costs

Adrian Jackson (Univ. Edinburgh)
15:15 16:00

Site Updates:

- IPCC Asia

- TACC Science Stories

- JSC Site Update

- KNL/OPA based KISTI 5th Supercomputer

- SSCC: Siberian supercomputer center for applied scientific computing


Taisuke Boku, University of Tsukuba

John Cazes, TACC

Bernd Mohr, Jülich Supercomputing Centre

Oh-Kyoung Kwon, KISTI Korea

Igor Chernykh, Siberian Supercomputer Center

16:00 16:30 Break  
16:30 17:00


DM-HEOM: A Portable and Scalable Solver-Framework for the Hierarchical Equations of Motion

Matthias Noack (ZIB)
17:00 17:55 Open Discussion: Quo Vadis IXPUG Thomas Steinke (ZIB)
17:55 18:00 Wrap-up  



Call for PAPERS: The submission process opened on March 7, 2018 and will close on April 15, 2018. April 29, 2018. All submitters should provide an abstract and FULL PAPER, uploaded to the IXPUG EasyChair site.  Notifications will be issued on May 20, 2018.  Please be sure to focus your content on the approach that was taken, obstacles encountered, solutions developed, performance results and next steps. 


Topics of interest are (but not limited to): sharing techniques in vectorization, memory, communications, thread and process management, multi-node application experiences, programming models, algorithms and methods, software environment and tools, benchmarking and profiling tools, visualization development, etc.


Important Dates:

         Call for Papers: March 14, 2018

         Deadline for submissions:  April 15, 2018  April 29, 2018 AoE  [Deadline extended]

         Final acceptance notification: May 20, 2018

        Conference Ready Paper: June 17, 2018

         Camera ready paper:  July 29, 2018 

Review Process

Reviewers are expected to make judgment on what was available at the time reviews were assigned. Subsequent updates to content may or may not be considered by the program committee as part of the selection decision. We encourage authors to exercise the freedom to use the time up until presentation and camera ready copy to provide the highest-quality product.

All submitted papers will be reviewed. We apply a standard single-blind review process, i.e., the authors will be known to reviewers. All submissions within the scope of the workshop will be peer-reviewed and will need to demonstrate quality of the results, originality and new insights, technical strength, and correctness. The submitted papers may not be published in or be in preparation for other conferences, workshops or journals.