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We have collected presentations from IXPUG workshops, annual meetings, and BOF sessions, and made them accessible here to view or download. You may search by event, keyword, science domain or author’s name. The database will be updated as new talks are made available.
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Search ResultShowing 1 - 10 of 498 Results
The drug discovery process currently employed in the pharmaceutical industry typically requires about 10 years and $2-3 billion to deliver one new drug. This is both too expensive and too slow, especially in emergencies like the COVID-19 pandemic. In silico methodologies need to be improved to better select lead compounds that can proceed to later stages of the drug discovery protocol accelerating the entire process. No single methodological approach can achieve the necessary accuracy with required efficiency. Here we describe multiple methodological and supporting infrastructural innovations at scale. Specifically, how we used TACC’s Frontera on > 8000 compute nodes to sustain 144M/hour docking hits, and to screen ?100 Billion drug candidates. These capabilities have been used by the US-DOE National Virtual Biotechnology Laboratory, and represent important progress towards improvement of computational drug discovery, both in terms of size of libraries screened, but also the possibility of generating training data fast enough for very powerful (docking) surrogate models. Shantenu Jha is the Chair of Computation & Data Driven Discovery Department at Brookhaven National Laboratory, and Professor of Computer Engineering at Rutgers University. His research interests are at the intersection of high-performance distributed computing and computational & data science. Shantenu leads the RADICAL-Cybertools project which are a suite of middleware building blocks used to support large-scale science and engineering applications. He was appointed a Rutgers Chancellor's Scholar (2015) and was the recipient of the inaugural Chancellor's Excellence in Research (2016) for his cyberinfrastructure contributions to computational science. He is a recipient of the NSF CAREER Award (2013), the Gordon Bell Award (2020) and several other prizes at SC'xy and ISC’xy, as well as the winner of IEEE SCALE 2018. More details can be found at: http://radical.rutgers.edu/shantenu
Keyword(s): COVID-19,in silico methodologies,TACC,Frontera,US-DOE,biotechnology,computational drug discovery,surrogate models
Author(s): Shantenu Jha Video(s): Read more | |Artificial Intelligence-Enabled Multi-Scale Simulations for COVID-19 Drug Discovery, IXPUG Mid-Year Workshop 2021 keynote presentation by Arvind Ramanathan, Argonne National Lab
Keyword(s): COVID-19,,AI/ML,RNA processing,accelerated simulations,statistical inference,DeepDrive MD,weighted ensemble simulations,heterogenous hardware,Stream-AI-MD,artificial intelligence
Author(s): Arvind Ramanathan Video(s): Read more | |SPMD / SIMD on GPUs
Keyword(s): SPMD,SIMD on GPUs
Author(s): Patrick Steinbrecher Video(s): Read more | |I have been collecting things which aren't taught in our SYCL (DPC++) book, and you won't get in a full day tutorial on SYCL (at least as taught thus far). In 30 minutes, I will share the collection as it stands today - and I will explain why these matter, and how they underscore the value of SYCL over CUDA because many of the nuances are new to us all because they help SYCL address XPUs (more than 'just GPUs') and they address the needs of being open for multivendor support.
Keyword(s): SYCL,DPC++,nuances
Author(s): James Reinders Video(s): Read more | |The high-performance computing (HPC) ecosystem increasingly supports heterogeneous architectures and customization. Field programmable gate arrays (FPGA) are among the options being considered due to their ability to both adapt to individual workloads and serve as prototype vehicles for application-specific accelerators. However, adoption has been limited due to the difficulty in programming these devices. To mitigate this, vendors are introducing frameworks based on embedded domain specific languages (eDSLs), such as SYCL. This work takes the first step in evaluating one of these new DSLs, DPC++, using DOE proxy applications to identify programmability gaps and performance on Intel FPGAs. Initial testing is being done with the MiniAMR application from the Mantevo suite, focusing on the 7-point stencil.
Keyword(s): FPGA Evaluation,oneAPI,Mantevo,SYCL,DPC++
Author(s): Nicholas Miller Video(s): Read more | |This lightning talk presents our work on parallelizing the epidemiological simulation model Episim. Episim combines a large-scale person-centric human mobility model with a mechanistic model of infection and a person-centric disease progression model. Movements of persons, including the intervening activities in which they may interact with others, can be directly taken from data. Episim can be used to evaluate different intervention strategies, such as closing educational facilities, reducing other out-of-home activities, wearing masks, or contact tracing. In general, the parallelization of agent-based models is challenging. Especially when the underlying social network is irregular and dynamic, they require frequent communication between the processing elements. In Episim, however, we were able to take advantage of the fact that people are not contagious on the same day they become infected, and therefore immediate health synchronization is not required.
Keyword(s): Epidemics,Agent-based modeling,Parallel programming
Author(s): Steffen Fuerst Video(s): Read more | |With discrete Intel GPUs entering the high performance computing landscape, there is an urgent need for production-ready software stacksfor these platforms. In this paper, we report how we prepare the Ginkgo math library for Intel GPUs by developing a kernel backed based on the DPC++ programming environment. We discuss conceptual differences to the CUDA and HIP programming models and describe workflows for simplified code conversion. We benchmark advanced sparse linear algebra routines utilizing the converted kernels to assess the efficiency of the DPC++ backend in the hardware-specific performance bounds, and compare the performance of basic building blocks against routines providing the same functionality that ship with Intel's oneMKL vendor library.
Keyword(s): oneAPI,Intel GPUs,Ginkgo,Math library,Ginkgo Math library,SpMV
Author(s): Terry Cojean Video(s): Read more | |This paper explores the process and results of converting an existing Fortran kernel to a Data Parallel C++ (DPC++) kernel with offload functionality while maintaining the main driver routine as Fortran. Obstacles and chosen solutions are discussed with intent to provide guidance to future developers. Initial performance comparisons are made between the original Fortran code, Fortran with OpenMP* offload, and DPC++ offload.
Keyword(s): DPC++,Mixed Language,Fortran,Heterogeneous Compute
Author(s): James Tullos, Christoph Bauinger Video(s): Read more | |The trifecta of high volumes of data, abundant compute availability on cloud and on-premise, and rapid algorithmic innovations enable data scientists and AI researchers to do fast experiments, prototyping, and model development at an accelerated pace that was never possible before. In this talk, we will touch upon a variety of software packages, libraries, and tools that can also help HPC practitioners push the envelope of applying AI in their application domains and simulations at-scale. We will cover examples and talk about how to create efficient end-to-end AI pipelines with large data sets in-memory, security, and other features through Intel-optimized software packages such as Intel® Distribution of Python, Intel® Optimized Modin, Intel® Optimized Sklearn, and XGBoost, as well as DL Frameworks such as Intel® Optimized Tensorflow and Intel® Optimized PyTorch tuned and enabled with new hardware features and instructions every new CPU generation.
Keyword(s): oneAPI,Modin,Intel® AI Analytics Toolkit,Intel® Distribution of Modin,Scikit-learn,XGBoost,Machine Learning,Census,PLAsTiCC,SigOpt
Author(s): Meena Arunachalam, Vrushabh Sanghavi Video(s): Performance Optimizations for End-to-End AI Pipelines Read more | |In this webinar we will demonstrate how an existing CUDA stencil application code can be migrated to DPC++ with the help of the Compatibility Tool. We will highlight and discuss the crucial differences between the two programming environments in the context of migrating the tsunami simulation easyWave. The discussion also includes steps for making the code to compliant with the SYCL standard. During the talk, we will also show that the migrated code can run on a wide range of platforms starting from CPUs, over GPUs, to FPGAs.
Keyword(s): oneAPI,SYCL,easyWave,heterogeneous architectures,Data Parallel C++,stencil kernels,Compatibility Tool,Unified Shared Memory,DPC++
Author(s): Marius Knaust, Steffen Christgau Video(s): Migrating from CUDA-only to Multi-Platform DPC++ Read more | |