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We have collected presentations from IXPUG workshops, annual meetings, and BOF sessions, and made them accessible here to view or download. You may search by event, keyword, science domain or author’s name. The database will be updated as new talks are made available.
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Search ResultShowing 1 - 10 of 388 Results
Software must be optimized for both Compute (including SIMD vector parallelism) and effective memory sub-system utilization to achieve scaled performance on modern hardware. In this talk we present state-of-the-art Intel Advisor Roofline performance model automation which helps to identify memory bottlenecks and balance between CPU and memory utilization. The talk will not only cover “cache-aware” Roofline implementation, but also new capabilities to produce DRAM (“original”) and multi-level (L1, L2, LLC, MCDRAM and DRAM – all de-coupled) Roofline model flavors in order to guide DRAM- or cache-bound applications optimization.
Keyword(s): Roofline
Author(s): NA Video(s): Optimize for Both Memory and Compute on Modern Hardware Using Roofline Model Automation in Intel® Advisor Read more | |Software must be optimized for both Compute (including SIMD vector parallelism) and effective memory sub-system utilization to achieve scaled performance on modern hardware. In this talk we present state-of-the-art Intel Advisor Roofline performance model automation which helps to identify memory bottlenecks and balance between CPU and memory utilization. The talk will not only cover “cache-aware” Roofline implementation, but also new capabilities to produce DRAM (“original”) and multi-level (L1, L2, LLC, MCDRAM and DRAM – all de-coupled) Roofline model flavors in order to guide DRAM- or cache-bound applications optimization.
Keyword(s): Roofline
Author(s): Zakhar Matveev Video(s): Optimize for Both Memory and Compute on Modern Hardware Using Roofline Model Automation in Intel® Advisor Read more | |Learn about Intel® Deep Learning Boost (Intel® DL Boost), and its Vector Neural Network Instructions (VNNI). These are a new set of Intel® Advanced Vector Extension 512 (Intel® AVX-512) instructions that are designed to deliver significantly more efficient Deep Learning inference acceleration. We will show a live demo of them in action and quickly show you how you can get started with Intel® DL Boost today.
Keyword(s): VNNI,DL-Boost,inferencing,cascade lake,int8
Author(s): Shailen Sobhee Video(s): Accelerate Your Inferencing with Intel® Deep Learning Boost Read more | |Distributed TensorFlow* Training with Intel® nGraph Library on Intel® Xeon® Scalable Processors
Keyword(s): Distributed training architecture,Scaling,Convergence,Synchronous SGD,Asynchronous SGD,Distributed training,Multi-node convergence
Author(s): Jianying Lang Video(s): Distributed TensorFlow* Training with Intel® nGraph Library on Intel® Xeon® Scalable Processors Read more | |ALCF Site Update: Update on Coming Exascale System and Preparing Science for Future Systems at All Scale
Keyword(s): Exascale
Author(s): David Martin Video(s): Read more | |ISC19 IXPUG Workshop: "Using FPGAs to Accelerate HPC & Data Analytics on Intel-Based Systems" Intro Slides
Keyword(s): IXPUG
Author(s): Thomas Steinke Video(s): Read more | |Stratix10 FPGA Cluster as Off-loaded Custom Computing Engine for Supercomputers
Keyword(s): Spatial Custom Computing
Author(s): Kentaro Sano Video(s): Read more | |High-Performance Computing with FPGAs
Keyword(s): Kernel Analysis
Author(s): Christian Plessl Video(s): Read more | |AI/ML High Performance Computing with FPGAs
Keyword(s): FPGA,Machine Learning,Deep Learning,Artificial Intelligence,one API,Deep Neural Network
Author(s): Jose Alvarez Video(s): Read more | |Exploring the Acceleration of the Met Office NERC Cloud Model Using FPGAs
Keyword(s): FPGA,Fortran,DRAM,BRAM,High Level Synthesis kernel,Advection kernels
Author(s): Nick Brown Video(s): Read more | |