Resources

We have collected presentations from IXPUG workshops, annual meetings, and BOF sessions, and made them accessible here to view or download. You may search by event, keyword, science domain or author’s name. The database will be updated as new talks are made available.

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Search ResultShowing 1 - 10 of 505 Results

IXPUG BoF at SC21 Jun 22, 2022

Best Practices for Benchmarking Diverse Architectures with Varied Workloads (agenda slide)

Keyword(s): IXPUG BoF at SC21 agenda slide

Author(s): David Martin
Video(s):
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IXPUG BoF at SC21 Jun 22, 2022

IXPUG Overview and Activities (IXPUG BoF at SC21)

Keyword(s): IXPUG overview and activities

Author(s): Thomas Steinke
Video(s):
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IXPUG BoF at SC21 Jun 22, 2022

A Simple Cost-model for Comparing Diverse Architectures

Keyword(s): cost model,diverse hardware,time-to-solution,memory footprint,result depreciation,compute cost,cost-per-run,Amdahl’s law

Author(s): Todd Evans
Video(s):
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IXPUG BoF at SC21 Jun 22, 2022

Best Practices for Benchmarking Diverse Architectures with Varied Workloads

Keyword(s): benchmarks,performance,double precision performance,Roofline Model,benchmark parameters,reproducibility,Continuous Benchmarking,Continuous Integration

Author(s): Hartwig Anzt
Video(s):
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IXPUG Webinar Series May 03, 2022

The Intel® Fortran Compiler is built on a long history of generating optimized code that supports industry standards while taking advantage of built-in technology for Intel® Xeon® Scalable processors and Intel® Core™ processors. Staying aligned with Intel's evolving and diverse architectures, the compiler now supports GPUs. This presentation will cover the compiler standards and path forward. There are two versions of this compiler. Both versions integrate seamlessly with popular third-party compilers, development environments, and operating systems. • Intel Fortran Compiler: provides CPU and GPU offload support • Intel Fortran Compiler Classic: provides continuity with existing CPU-focused workflows Features: • Improves development productivity by targeting CPUs and GPUs through single-source code while permitting custom tuning • Supports broad Fortran language standards • Incorporates industry standards support for OpenMP* 4.5, and initial OpenMP 5.0 and 5.1 for GPU offload • Uses well-proven LLVM compiler technology and Intel's history of compiler leadership • Takes advantage of multicore, Single Instruction Multiple Data (SIMD) vectorization and multiprocessor systems with OpenMP, automatic parallelism, and coarrays Speaker: Ron Green is the manager of the Intel Fortran OpenMP and Runtime Library development team. He is a moderator for the Intel Fortran Community Forum and is an Intel Developer Zone “Black Belt”. He has extensive experience as a developer and consultant in HPC for the past 30+ years and has been with Intel’s compiler team for thirteen years. His technical interest area is in parallel application development with a focus on Fortran programming.

Keyword(s): HPC,Fortran,Intel Fortran® Compiler,oneAPI,Intel® oneAPI,OpenMP,IFORT,IFX,Intel® Xeon® Scalable processors,Intel® Core™ processors

Author(s): NA
Video(s): , Intel Fortran Compilers: A Tradition of Trusted Application Performance
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IXPUG Webinar Series Mar 23, 2022

This presentation will provide a technical overview of Distributed Asynchronous Object Store (DAOS), a software-defined object store designed from the ground up for massively distributed Non-Volatile Memory (NVM), including Intel® Optane™ DC persistent memory and Intel Optane DC SSDs. This presentation will also introduce the performance and explain main features of DAOS.

Keyword(s): DAOS,Intel® Optane™,Storage,POSIX,PyDAOS

Author(s): Zhen Liang
Video(s): DAOS: Storage Innovations Driven by Intel® Optane™
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IXPUG Webinar Series Dec 13, 2021

For shared memory programming of GPGPU systems, users either have to manually run their domain decomposition along available GPUs as well as GPU Tiles. Or leverage implicit scaling mechanisms that transparently scale their offload code across multiple GPU-Tiles. The former approach can be cumbersome, and the latter approach is not always the best performing one. The Intel MPI library can take that burden from users by enabling the user to program only for a single GPU / Tile and leave the distribution to the library. This can make HPC / GPU programming much easier. Therefore, Intel® MPI does not just allow to pin individual MPI ranks to individual GPUs or Tiles, but also allows users to pass GPU memory pointers to the library. Download documentation at https://software.intel.com/content/www/us/en/develop/documentation/mpi-developer-reference-linux/top/environment-variable-reference/gpu-support.html

Keyword(s): Intel® MPI Library,GPU,Multi-GPU

Author(s): NA
Video(s): Multi-GPU Programming—Scale-Up and Scale-Out Made Easy, Using the Intel® MPI Library
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IXPUG Webinar Series Dec 02, 2021

The drug discovery process currently employed in the pharmaceutical industry typically requires about 10 years and $2-3 billion to deliver one new drug. This is both too expensive and too slow, especially in emergencies like the COVID-19 pandemic. In silico methodologies need to be improved to better select lead compounds that can proceed to later stages of the drug discovery protocol accelerating the entire process. No single methodological approach can achieve the necessary accuracy with required efficiency. Here we describe multiple methodological and supporting infrastructural innovations at scale. Specifically, how we used TACC’s Frontera on > 8000 compute nodes to sustain 144M/hour docking hits, and to screen ?100 Billion drug candidates. These capabilities have been used by the US-DOE National Virtual Biotechnology Laboratory, and represent important progress towards improvement of computational drug discovery, both in terms of size of libraries screened, but also the possibility of generating training data fast enough for very powerful (docking) surrogate models. Shantenu Jha is the Chair of Computation & Data Driven Discovery Department at Brookhaven National Laboratory, and Professor of Computer Engineering at Rutgers University. His research interests are at the intersection of high-performance distributed computing and computational & data science. Shantenu leads the RADICAL-Cybertools project which are a suite of middleware building blocks used to support large-scale science and engineering applications. He was appointed a Rutgers Chancellor's Scholar (2015) and was the recipient of the inaugural Chancellor's Excellence in Research (2016) for his cyberinfrastructure contributions to computational science. He is a recipient of the NSF CAREER Award (2013), the Gordon Bell Award (2020) and several other prizes at SC'xy and ISC’xy, as well as the winner of IEEE SCALE 2018. More details can be found at: http://radical.rutgers.edu/shantenu

Keyword(s): COVID-19,in silico methodologies,TACC,Frontera,US-DOE,biotechnology,computational drug discovery,surrogate models

Author(s): Shantenu Jha
Video(s): IMPECCABLE: A Dream Pipeline for High-Throughput Virtual Screening, or a Pipe Dream?
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IXPUG Mid-Year Workshop 2021 Jul 15, 2021

Artificial Intelligence-Enabled Multi-Scale Simulations for COVID-19 Drug Discovery, IXPUG Mid-Year Workshop 2021 keynote presentation by Arvind Ramanathan, Argonne National Lab

Keyword(s): COVID-19,,AI/ML,RNA processing,accelerated simulations,statistical inference,DeepDrive MD,weighted ensemble simulations,heterogenous hardware,Stream-AI-MD,artificial intelligence

Author(s): Arvind Ramanathan
Video(s):
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IXPUG Mid-Year Workshop 2021 Jun 21, 2021

SPMD / SIMD on GPUs

Keyword(s): SPMD,SIMD on GPUs

Author(s): Patrick Steinbrecher
Video(s):
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