Where to access Xeon Phi Systems
A handful of US and international laboratories and computing centers have made their KNL systems available for researchers. Use the links below to learn more about those systems and how to access them. More centers will be added to this list as the systems come online.
- NERSC - The NERSC Exascale Science Applications Program (NESAP)
- Argonne National Laboratory - Early Science Program (ESP)
- TACC - request an allocation through the TACC User Portal or through an XSEDE allocation.
- PRACE KNL system (MARCONI)
- Riken AICS (Japan)
High Performance Computing Development Tools and Libraries
- Intel HPC Tools
- Performance and Debugging Tools at NERSC
- Link to a publicly-writable page at which we encourage you to add links and very brief descriptions/analyses of productivity tools, analysis tools libraries and applications
- We created a github site for code examples, tests, etc. Thanks to Srinath Vadlamani and Hans Johannsen for setting this up!
Entries for PvFMM, NAMD and Chroma were moved to the tools, libraries and applications page (link).
Preparing your code for KNL
The "Preparing your software for KNL" document provides an overview of tools, techniques, best known methods, etc. to help enable codes for KNL. The content covers:
- Compiling your software
Intel® Software Development Emulator (Intel® SDE)
Checking Vectorization with Intel® Advisor (aka. Intel® AVX-512)
High-Bandwidth MCDRAM (aka. Fast Memory)
Characterization is sometimes critical in assessing the degree of tuning achieved vs. headroom for performance improvement, and in understanding what the remaining bottlenecks are.
Vectorization effectiveness: A set of metrics, tools and procedures for assessing the effectiveness of vectorization were developed for and presented at ISC'15's IXPUG workshop. A document describing metrics, tools and measurement techniques is here, along with a presentation. Some results from ISC'15 are available here and here.
DRAM sensitivity to latency and bandwidth: A set of metrics, tools and procedures for assessing the sensitivity to DRAM latency and bandwidth were developed for and presented at ISC'15's IXPUG workshop. A document describing metrics, tools and measurement techniques is here, along with a presentation. Some results from ISC'15 are available here.