ISC19 IXPUG Workshop


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ISC19 IXPUG Workshop: "Using FPGAs to Accelerate HPC & Data Analytics on Intel-Based Systems"


Location: Frankfurt, Germany (Marriott, room Megabyte)

Date & Time: Thursday, June 20, 2019, 2:00-6:00 p.m.

Registration: The workshop is held in conjunction with the ISC 2019 in Messe Frankfurt. To attend the IXPUG workshop, you must register through ISC19 website specifically for workshops.


Event Description: The workshop will bring together software developers, scientists, academia, and industry luminaries to share learnings around the integration and use of FPGA devices in HPC, Data Analytics, and Artificial Intelligence (Machine Learning and Deep Learning) workloads in Intel-based HPC systems. The workshop will cover strategies for migrating workloads onto FPGAs, performance comparisons, aspects of productivity, performance portability, and scalability. Objectives of the workshop: 1.) using FPGAs on Intel-based systems and scientific achievements, 2.) FPGA-related trends and challenges, and 3.) foster collaborations and strengthen the community of FPGA enthusiasts using Intel-based HPC systems.


Agenda: Please note that the agenda is subject to change.

Start End Title Speaker* and Authors Presentations
14:00  14:05 Welcome Thomas Steinke PDF
14:05 14:45 Keynote: High-Performance Computing with FPGAs Prof. Dr. Christian Plessl, Universität Paderborn PDF
14:45 15:15 Paper Presentation: Acceleration of Scientific Deep Learning Models on Heterogeneous Computing Platform with Intel® FPGAs Chao Jing, David Ojika, Thorsten Kurth, Prabhat, Sofia Vallecorsa, Bhavesh Patel, and Herman Lam PDF
15:15 15:45 Paper Presentation: Accelerating the MET Office NERC Cloud Model Using FPGAs Nick Brown PDF
15:45 16:00 FPGA Site: Cygnus FPGA+GPU Accelerated Cluster at University of Tsukuba Taisuke Boku  
16:00 16:30 Break    
16:30 17:05 Invited Talk: Stratix10 FPGA Cluster as Off-Loaded Custom Computing Engine for Supercomputers Kentaro Sano, RIKEN Center for Computational Science (R-CCS) PDF
17:05 17:20 Research and Development Activities in SHREC@UF* using Intel FPGAs Herman Lam PDF
17:20 17:30

Site Updates:





David Martin

Brandon Cook

Thomas Steinke


Argonne PDF 


17:30 18:00 Invited Talk: An Overview of Heterogeneous Solutions for Artificial Intelligence and Data Analytics José Roberto Alvarez, Sr. Director, PSG CTO Office, Intel Corporation PDF
18:00   Closing: Wrap-Up Thomas Steinke  



Call for Papers: The submission process will close on April 14, 2019 AoE. All submitters should provide content that represents a FULL PAPER via the IXPUG EasyChair website. All accepted technical papers will be given roughly 10-15 minutes in length to present a "Lightning Talk". An interactive Panel Session (~30 minutes) with representatives from the global developer community, tool chain developers, as well as standardization bodies (OpenMP, OpenCL, etc.). Notifications will be sent to submitters by April 24, 2019 AoE (new date!). Please be sure to focus your content on the approach that was taken, obstacles encountered, solutions developed, performance results and future work aspirations.


Instructions for Papers:


Topics of Interest are (but not limited to): Sharing field-programmable gate array (FPGA), FPGA programming environments and abstraction tools, FPGA programming models, comparison of FPGA performance vs traditional or GPU hardware, embedded memory architectures, algorithmic techniques and mapping to FPGAs, machine learning algorithms on FPGAs, FPGA offload techniques, FPGA interfaces to traditional hardware, integrating FPGAs into an existing HPC environment. 

Keywords: field-programmable gate array (FPGA), reconfigurable architectures, HPC, Artificial Intelligence (machine learning and deep learning) applications performance, FPGAs using Intel-based technology, benchmarking, programming environments, FPGA tools and techniques. 


Review Process: All submitted papers will be reviewed and we will apply the standard single-blind review process (i.e. the authors will be known to reviewers). The assignment of reviewers from the Program Committee avoids conflicts of interest. All submissions within the scope of the workshop will be peer-reviewed and will need to demonstrate quality of results, originality, new insights, technical strength, and ensure correctness. The submitted papers may not be published in or be in preparation for the other conferences, workshops or journals.



Important Dates:

  • Deadline for Paper Submissions and Uploaded to IXPUG EasyChair: April 14, 2019
  • Final Paper Acceptance Notifications: April 24, 2019 (new date!)
  • Final Paper Submission and Uploaded to IXPUG EasyChair: June 19, 2019



  • Thomas Steinke, IXPUG President (Zuse Institute Berlin)
  • Estela Suarez (Juelich Supercomputing Centre)
  • Taisuke Boku (University of Tsukuba)
  • Nalini Kumar (Intel Corporation)
  • David Martin (Argonne National Laboratory)


Review Committee:

  • R. Glenn Brook, IXPUG Vice-President (University of Tennessee, Knoxville)
  • Richard Gerber (NERSC/LBNL)
  • Clay Hughes (SNL)
  • Kent Milfeld (TACC)
  • David Keyes (KAUST)
  • John Pennycook (Intel Corporation)
  • Vit Vondrak (VSB-Technical University of Ostrava)
  • James Lin (Shanghai Jiao Tong University)
  • Fabio Affinito (CINECA)
  • Vladimir Mironov (Lomonosov Moscow State University)
  • Sergi Siso (UK Science & Technology Facilities Council)