IXPUG HPC Asia 2022


Conference Dates: January 12-14, 2022

Workshop Date: January 14, 2022 (13:30-17:30 JST; all times are in JST)

Location: HPC Asia 2022 (International Conference on HPC in Asia-Pacific Region)Fully Online Conference; please register to attend.

Event Description:

The Intel eXtreme Performance Users Group (IXPUG) is an active community led forum for sharing industry best practices, techniques, tools, etc. for maximizing efficiency on Intel platforms and products. IXPUG Workshop at HPC Asia 2022 is an open workshop on high performance computing applications, systems, and architecture with Intel technologies. This is a half-day workshop with invited talks and contributed papers. The workshop aims to bring together software developers and technology experts to share challenges, experiences and best-practice methods for the optimization of HPC, Machine Learning, and Data Analytics workloads on Intel® Xeon® Scalable processors, Intel® FPGA, and any related hardware/software platforms. The workshop will cover application performance and scalability challenges at all levels—from intra-node performance up to large-scale compute systems. Any research aspect related to Intel HPC products is welcome to be presented in this workshop.

Workshop Agenda

All times are shown in JST (Japan Standard Time, UTC+9). Final presentations will be made accessible to download at https://www.ixpug.org/resources after the workshop.

Time Title and Authors Presenter Presentation
13:30 Opening Remarks Toshihiro Hanawa, Workshop Chair


Session 1 Chair: Toshihiro Hanawa



Keynote: Stepping Forward to the Post Dennard Era Together to Achieve More and Do It Faster

We aren’t advancing our computing performance as quickly as we have been, and quite frankly it means we aren’t getting as much accomplished as we would like. The breakdown of Dennard Scaling and subsequent power inefficiencies are the real culprit. Intel has new and novel products and architectures to lead us past this performance plateau, but it is really open standards and partnerships that will enable the faster innovations required to solve the most challenging problems. Together, we’ll step forward to the Post Dennard Era and advance science and society.

Chris Lindahl, Intel Corporation


Talk 1: ParaFold: Paralleling AlphaFold for Large-Scale Predictions

Bozitao Zhong, Xiaoming Su, Minhua Wen, Sicheng Zuo, Liang Hong, James Lin (Shanghai Jiao Tong University)

James Lin


Talk 2: A Process Management Runtime with Dynamic Reconfiguration

Shinji Sumimoto (Fujitsu Ltd.), Toshihiro Hanawa (The University of Tokyo), Kengo Nakajima (The University of Tokyo/RIKEN R-CCS)

Shinji Sumimoto  
15:20 Coffee Break (20 min.)    

Session 2 Chair: James Lin



Invited Talk: SYCL Programming for Collaboration of x86 and Friends

Today, so-called accelerator computing has already become commonplace, meaning that HPC programmers need to well exploit both parallelism and heterogeneity of their target applications and systems to achieve high sustained performance in practice. In the upcoming exascale computing era, an HPC system could be equipped with more kinds of custom hardware components, and we need a standard programming interface to make a good collaboration of those components. SYCL and its extension, Data Parallel C++, are the most promising candidate of such an interface. In this presentation, I will talk about a new "friend" in the x86 world, named NEC vector engine, whose computing power can be used from x86 applications via our SYCL implementation. As x86 and vector processors have their own strengths, we can expect to achieve higher performance by assigning the right processor to the right task.

Hiroyuki Takizawa, Tohoku University


Talk 3: Offloading Transprecision Calculation Using FPGA

Tadayoshi Hara, Toshihiro Hanawa (The University of Tokyo)

Toshihiro Hanawa


Talk 4: Exploring Communication-Computation Overlap in Parallel Iterative Solvers on Manycore CPUs using Asynchronous Progress Control

Masashi Horikoshi (Intel Corporation), Balazs Gerofi (RIKEN R-CCS), Yutaka Ishikawa (National Institute of Informatics), Kengo Nakajima (The University of Tokyo/RIKEN R-CCS)

Masashi Horikoshi

17:20 Closing Remarks

Toshihiro Hanawa, Workshop Chair


Call for Papers (closed)

IXPUG is soliciting submissions for technical presentations on innovative work using Intel architecture from users in academia, industry, government/national labs, etc. describing original discoveries, experiences, and methods for obtaining efficient and scalable use of heterogeneous systems. IXPUG welcomes full papers up to 18 pages within 30 minutes presentation and also welcomes short papers 7-8 pages within 15 minutes presentation. Please submit your paper to IXPUG via EasyChair. We welcome topics on Intel architecture, including but not limited to the following topics of interest:

Paper Topics of Interest:

  • Artificial Intelligence (Machine Learning / Deep Learning)
  • Application porting and performance optimization
  • Vectorization, memory, communications, thread, and process management
  • Multi-node application experiences
  • Programming models, algorithms, and methods
  • Software environment and tools
  • Benchmarking and profiling tools
  • Visualization development
  • FPGA applications and system software

Paper Format:

All papers must be original and not simultaneously submitted to another journal or conference. The following paper categories are welcome:

  • Regular papers up to 18 pages with single column (in ACM submission format)
  • Short papers 7-8 pages with single column (in ACM submission format)

Note: as ACM new style, submission is single-column while publishing is two-column. Both Word and LaTeX have a single column. Refer to the ACM Proceedings Template which can be obtained at: http://www.acm.org/publications/proceedings-template

Important Dates:

  • Paper due: November 15, 2021 (closed)
  • Notification of acceptance: November 22, 2021
  • Camera-ready due: November 29, 2021
  • Workshop: January 14, 2022 (afternoon, JST; detail time is TBD)

Paper Submission Site: https://easychair.org/cfp/IXPUGWorkshopatHPCAsia2022


All accepted papers will be included in ACM Digital Library as a part of the HPC Asia 2022 Workshop Proceedings. Also, IXPUG Workshop at HPC Asia 2022 final presentations will be made accessible to download at https://www.ixpug.org/resources.

Organizing Committee:

  • Chair: Toshihiro Hanawa (The University of Tokyo)

Program Committee:

  • Aksel Alpay (Heidelberg University)
  • R. Glenn Brook (University of Tennessee, Knoxville)
  • Melyssa Fratkin (Texas Advanced Computing Center, The University of Texas at Austin)
  • Clay Hughes (Sandia National Laboratory)
  • David Keyes (King Abdullah University of Science & Technology)
  • Nalini Kumar (Intel Corporation)
  • James Lin (Shanghai Jiao Tong University)
  • Hatem Ltaief (King Abdullah University of Science & Technology)
  • David Martin (Argonne National Laboratory)
  • Amit Ruhela (Texas Advanced Computing Center, The University of Texas at Austin)
  • Thomas Steinke (Zuse Intitute Berlin)
  • Joe Zerr (Los Alamos National Laboratory)

Questions? All questions for workshop paper submission and organization should be sent to This email address is being protected from spambots. You need JavaScript enabled to view it.General questions should be sent to This email address is being protected from spambots. You need JavaScript enabled to view it..