IXPUG HPC Asia 2018

 


IXPUG Workshop at HPC Asia 2018

 Date: January 31, 2018

 

Location: International Conference on High Performance Computing in Asia-Pacific Region, Tokyo Japan at the Akihabara UDX Bldg. 4-14-1, Sotokanda,Chiyoda-ku,Tokyo

 

Registration: all attendees must register through the HPC Asia 2018 Conference website. The deadline for early registration is January 15, 2018 (JST). All payments must be made in Japanese Yen (JPY).

 

Event Description: The Intel Xeon Phi Users Group (IXPUG) is an active community led forum for sharing industry best practices, techniques, tools, etc. for maximizing efficiency on Intel platforms and products. This is a half day workshop with contributed papers and key note talks. Any research aspect related to Intel Xeon Phi is welcome to present to share this advanced technology for high performance computing.

 

Travel Details:

      Visa Requirements: Please contact This email address is being protected from spambots. You need JavaScript enabled to view it. for visa inquiries.

      Hotel Recommendations: nearby hotels suggestions can be found HERE.


 

Call for Presentations: The submission process closed on December 13, 2018.

 

Important Dates:

Abstracts Submission Deadline: December 13, 2017 (AoE)

Presenters notified: December 20, 2017 (AoE)

Final presentations: January 31, 2018

 

 

Local Organizer: Please feel free to contact Taisuke BOKU, This email address is being protected from spambots. You need JavaScript enabled to view it. for questions regarding the workshop.

 

Keynote presented by Hiroshi Nakashima, Kyoto University on "Vectorization Quality: How well is your C code compiled?": Performance of your program on Xeon Phi processors heavily relies on the degree of vectorization of your loops, of course.  In the first place this degree depends on the nature of the loop body, e.g., free from (complicated) recurrences and conditionals, but the decisive factor is the ability of your compiler to recognize the vectorizability and then to generate efficient executable exploiting AVX-512 instructions.  In this talk, various examples of vectorizable loops written in C without intrinsics or directives are shown, to evaluate the quality of their machine codes generated by various compilers and to discuss the direction of improvements of programming, compilers and (micro)architecture.

 

Event Agenda: 

Start

End

Title

Author(s)

Presentation

13:00

13:05

Opening Remarks

Taisuke BOKU, Univ of Tsukuba

 

13:05

13:50

Keynote: "Vectorization Quality: How well is your C code compiled?"

Hiroshi Nakashima, Kyoto University

 

13:50

14:20

"Performance Evaluation for Omni XcalableMP Compiler on Many-core Cluster System based on Knights Landing"

Masahiro Nakao, Hitoshi Murai, Taisuke Boku and Mitsuhisa Sato

 

14:20

14:40

"Optimizing Two-Electron Repulsion Integral Calculation on Knights Landing Architecture"

Yingqi Tian, Bingbing Suo, Yingjin Ma and Zhong Jin

 

14:40

15:00

"Scaling Collectives on Large Clusters of Intel(R) Architecture Processors"

Masashi Horikoshi, Larry Meadows, Tom Elken, Pradeep Sivakumar, Edward Mascarenhas, James Erwin, Dmitry Durnov, Alexander Sannikov, Toshihiro Hanawa and Taisuke Boku

 

15:00

15:20

Coffee Break

15:20

15:50

Invited Talk "Xeon Phi Roadmap”

Joseph C. Curley, Intel

 

15:50

16:10

"OpenMP-based parallel implementation of matrix-matrix multiplication on the Intel Knights Landing"

Roktaek Lim, Yeongha Lee, Raehyun Kim and Jaeyoung Choi

 

16:10

16:30

"Multiple Endpoints for Improved MPI Performance on a Lattice QCD Code"

Larry Meadows, Ken-Ichi Ishikawa, Taisuke Boku and Masashi Horikoshi

 

16:30

16:50

"Real Test Cases Targeted Optimizations of VLPL-S Particle-in-cell Code on Knights Landing"

Minhua Wen, Min Chen and James Lin

 

16:50

17:00

Closing Remarks

Joseph C. Curley, Intel