IXPUG Annual Conference 2023

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IXPUG Annual Conference 2023

Hosted by Intel Corporation

Conference Dates: September 21-22, 2023

Location: Intel headquarters SC12 Auditorium, 3600 Juliette Lane, Santa Clara, CA 95054 in-person and virtual

Registration: https://cvent.me/v9BED9?RefId=IXPUG2023 The event is open to all audiences, attending in-person or virtually, but all attendees must register.

Sessions Preview: https://onlinexperiences.com/Launch/Event.htm?ShowKey=236392 (register to view)

 

Event Description

IXPUG Annual Conference 2023 is a two-day gathering of HPC and AI experts featuring keynotes, tech talks, lightning talks, site updates, and more. The event welcomes software developers, scientists, researchers, academics, systems analysts, students, and end-users who want to share with and learn from our vibrant, global community via technical discussion and networking. With the growing convergence of HPC and AI, challenges surrounding application performance and scalability will be covered across all levels, including tuning and optimization of diverse sets of applications on HPC systems. Topics are wide-ranging, including system hardware beyond the processor (memory, interconnects, etc.), accelerators (e.g., GPUs, AI accelerators, FPGAs), as well as topics related to oneAPI, tools, programming models, HPC and AI workloads, and more. Key themes: High performance computing, heterogeneous computing, artificial intelligence, visualization, memory, I/O, and storage.

Keynote Speakers

  • Uri Elzur, Intel Corporation "UltraEthernet – A Unified Network for HPC and AI"
  • Abhishek Bagusetty, Argonne National Laboratory "Tuning for Aurora"

Agenda

All times are shown in Pacific Daylight Time (PDT). Event details are subject to change. Registration is required.

Thursday, September 21:

8:00-9:00 a.m. In-person check-in and continental breakfast

Day 1 Keynote and Future Technologies | Session Chair: Amit Ruhela, Texas Advanced Computing Center

9:00-9:10 a.m. Conference Welcome and Opening Remarks
Presenters: Nalini Kumar, Intel Corporation; Amit Ruhela, Texas Advanced Computing Center

9:15-9:55 a.m. Keynote: UltraEthernet – A Unified Network for HPC and AI (Slides)
Presenter: Uri Elzur, Intel Corporation

10:00-10:25 a.m. Tech Talk: CXL Memory as Persistent Memory for Disaggregated HPC: A Practical Approach (Slides)
Presenter: Yehonatan Fridman, Ben-Gurion University, NCRN
Co-Authors: Suprasad Mutalik Desai, Intel Corporation; Navneet Singh, Intel Corporation; Thomas Willhalm, Intel Corporation; Gal Oren, Technion, NRCNC

10:30-10:45 a.m. Break

Molecular Dynamics and GPUs | Session Chairs: Clay Hughes, Sandia National Laboratories; David Martin, Argonne National Laboratory

10:45-11:25 a.m. Tech Talk: Porting RT-TDDFT Codes for GPU Accelerated Architectures (Slides)
Presenter: Taufeq Mohammed Razakh, University of Southern California
Co-Authors: Ye Luo, Argonne National Laboratory; Aiichiro Nakano, University of Southern California

11:30-11:45 a.m. Lightning Talk: Path to Exascale Material Simulation on Aurora Supercomputer (Slides)
Presenter: Ye Luo, Argonne National Laboratory
Co-Authors: Thomas Applencourt, Argonne National Laboratory; Jeongnim Kim, Intel Corporation

11:50 a.m.-12:15 p.m. Tech Talk: SYCL for Performance and Portability: A Molecular Dynamics Case Study (Slides)
Presenter: Andrey Alekseenko, SciLifeLab, KTH Royal Institute of Technology

12:15-12:30 p.m. Lightning Talk: Compiler Approach To Optimize DFT Sinusoidal Computation (Slides)
Presenter: Chen Cheng, Intel Corporation
Co-Authors: Wenju He, Intel Corporation; Ruqiu Cao, Intel Corporation

12:30-1:30 p.m. In-person lunch

AI, Libraries, GPUs, and CPUs | Session Chair: Nalini Kumar, Intel Corporation

1:30-1:55 p.m. Tech Talk: Scope Is All You Need: Transforming LLMs for HPC Code (Slides)
Presenter: Gal Oren, Technion, NRCN
Co-Authors: Tal Kadosh, Ben-Gurion University, IAEC; Niranjan Hasabnis, Intel Labs; Vy A. Vo, Intel Labs; Nadav Schneider, Ben-Gurion University, IAEC; Neva Krien, Independent Researcher; Abdul Wasay, Intel Labs; Nesreen Ahmed, Intel Labs; Ted Willke, Intel Labs; Guy Tamir, Intel Corporation; Yuval Pinter, Ben-Gurion University; Timothy Mattson, (Retired) Intel Corporation

2:00-2:25 p.m. Tech Talk: Intel® XeTLA: Templates Based Linear Algebra Library for Intel Xe GPU (Slides)
Presenter: Fangwen Fu, Intel Corporation
Co-Authors: Patric Zhao, Intel Corporation; Xiaodong Qiu, Intel Corporation; Eric Lin, Intel Corporation; Hong Jiang, Intel Corporation

2:30-2:55 p.m. Tech Talk: Distributed Ranges: A Model for Distributed Data Structures, Algorithms, and Views (Slides)
Presenter: Benjamin Brock, Intel Corporation
Co-Authors: Robert Cohn, Intel Corporation; Suyash Bakshi, Intel Corporation; Tuomas Karna, Intel Corporation; Jeongnim Kim, Intel Corporation; Mateusz Nowak, Intel Corporation; Lukasz Slusarczyk, Intel Corporation; Kacper Stefanski Intel Corporation; Timothy Mattson, (Retired) Intel Corporation

3:00-3:25 p.m. Tech Talk: Intel's Next Generation Datacenter CPU Architecture and the Performance-Core (P-Core)/Efficient-Core (E-Core) Processors Built on this Common Foundation (Slides)
Presenter: Krishna Vinod, Intel Corporation

3:30-4:00 p.m. Break

Site Updates | Session Chair: Glenn Brook, Cornelis Networks

4:00-4:15 p.m. Site update: King Abdullah University of Science & Technology ()
Presenter: Hatem Ltaief, King Abdullah University of Science & Technology

4:15-4:30 p.m. Site update: Argonne National Laboratory (Slides)
Presenter: David Martin, Argonne Leadership Computing Facility, Argonne National Laboratory

4:30-4:45 p.m. Site update: Texas Advanced Computing Center (Slides)
Presenter: John Cazes, Texas Advanced Computing Center

4:45-5:00 p.m. Conference Day 1 Closing Remarks
Presenter: Glenn Brook, Cornelis Networks

5:30-7:30 p.m. In-person networking reception sponsored by Cornelis Networks at Bar Sereno – Element Santa Clara

Friday, September 22:

8:00-9:00 a.m. In-person check-in and continental breakfast

Day 2 Keynote, SYCL/DNN, AI, CPUs, and SW Tools | Session Chairs: David Martin, Argonne National Laboratory; Glenn Brook, Cornelis Networks

9:00-9:10 a.m. Conference Day 2 Welcome and Opening Remarks
Presenters: Glenn Brook, Cornelis Networks; David Martin, Argonne Leadership Computing Facility, Argonne National Laboratory

9:15-9:55 a.m. Keynote: Tuning for Aurora (Slides)
Presenter: Abhishek Bagusetty, Argonne Leadership Computing Facility, Argonne National Laboratory

10:00-10:15 a.m. Lightning Talk: Loop Vectorization for SYCL Single Task (Slides)
Presenter: Wenwan Xing, Intel Corporation
Co-Authors: Wenju He, Intel Corporation; Wenjuan Xu, Intel Corporation

10:15-10:30 a.m. Lightning Talk: Introducing High Performance Computing to Chemists in Africa with the DevCloud (Slides)
Presenters: Benson Muite, Kichakato Kizito; Annajiat Alim Rasel, BRAC University
Co-Authors: Divya Bhikharee, University of Mauritius; Ponnadurai Ramasami, University of Mauritius

10:30-11:00 a.m. Break

Tools and GPUs | Session Chair: Amit Ruhela, Texas Advanced Computing Center

11:00-11:45 a.m. Tech Talk: Profiling Large-Scale Heterogeneous Applications with Intel® Vtune™ Profiler (Slides)
Presenter: Xiao Zhu, Intel Corporation
Co-Authors: Rupak Roy, Intel Corporation; Kevin O'Leary, Intel Corporation; Noah Clemons, Intel Corporation; Ying Song, Intel Corporation; Pallavi Gundawar, Intel Corporation

11:50 a.m.-12:35 p.m. Tech Talk: Kairos: Innovation in Advancing HPC and AI Application Performance Analysis (Slides)
Presenters: Antonio Valles, Intel Corporation; Rebecca David, Intel Corporation

12:40-1:00 p.m. Conference Closing Remarks
Presenter: Amit Ruhela, Texas Advanced Computing Center

1:00 p.m. In-person lunch

Air Travel and Lodging

The IXPUG conference will be held at Intel headquarters SC12 Auditorium, 3600 Juliette Lane, Santa Clara, CA 95054. San José Mineta International Airport (SJC) is the closest airport. These hotels have special rates for IXPUG conference attendees:

Submission Guidelines
If you are interested in presenting a talk, or technical session, please submit a short abstract by Friday, August 18, 2023 (AoE) via EasyChair. While in-person presentations are preferred, pre-recorded videos will be allowed as presentations in exceptional cases. Published or work-in-progress research in respective areas is encouraged and presenters retain the right to publish elsewhere. All final presentations are due by September 19, 2023 AoE (updated).

Topics of Interest

  • Application characterization on emerging technologies: processors (Intel® Xeon® Scalable processors, Intel® GPUs, Intel® FPGAs, etc.), CXL-attached memory, OPA, etc.
  • Experience with incorporating machine learning and deep learning in HPC applications and workflows including surrogate modeling, foundational models, augmented experiment design, etc.
  • Performance analysis, optimization, and best practices, and implications of HPC and HPC-AI workload behavior on system design at extreme scale (Power, Reliability, Scalability, Performance, Processor Design, Memory System, I/O)
  • Software environments and tools for computing at extreme scale (Instrumentation, Debugging/Correctness, Thread and Process Management, Libraries and Language Development)
  • Experience using extreme scale systems: Usability, In-situ Visualization, Programming Challenges, Algorithms and Methods, etc.

Important Dates
Abstract submission deadline: August 18, 2023 (AoE)
Acceptance notification: August 25, 2023
Presenters’ confirmation deadline: September 1, 2023
Presenters’ consent deadline: September 1, 2023
Final presentations due from speakers: September 19, 2023 AoE (updated)

Accepted speakers: Upload your final presentation files via EasyChair by September 19 AoE. The presentation slides must be in PowerPoint format (file extension .pptx or .ppt) with 16:9 aspect ratio. Videos should not be embedded in the slides. If video is part of your presentation, include a placeholder slide at the point the video will be shown. Provide the video as a separate file. Videos must be in .mov or .mp4 format. Contact This email address is being protected from spambots. You need JavaScript enabled to view it. with any questions.

IXPUG sessions (event dates): September 21-22, 2023

IXPUG 2023 Program Committee

  • Glenn Brook, Cornelis Networks
  • Michael Hennecke, Intel Corporation
  • Nalini Kumar, Intel Corporation
  • David Martin, Argonne National Laboratory
  • Christopher Mauney, Los Alamos National Laboratory
  • Amit Ruhela, Texas Advanced Computing Center (TACC)

Publication
IXPUG Annual Conference 2023 presentations will be published on the IXPUG website. All presenters will retain the copyright to their work.

Contact
Questions? Email This email address is being protected from spambots. You need JavaScript enabled to view it.