IXPUG 2016


Experts from around the world met at Argonne National Laboratory for the IXPUG 2016 Annual US Meeting (IXPUG2016). They shared  experiences with Xeon Phi-based systems, and learned how to optimize software for manycore machines.

Meeting Highlights:

  • Monday - Tutorials on MPI and OpenMP, Programming with Xeon Phi
  • Tuesday - Plenary Talks by HPC centers on Deployment and Early Science, Keynotes by Rick Stevens (Argonne) and Joe Curley (Intel)
  • Wednesday - Technical Talks on Applications, Memory Models and Tuning, Tutorials on Optimization
  • Thursday - Technical Talks on Tools, Techniques and Visualization, Keynote by Jim Tullos (Intel)

Survey: Meeting attendees, please provide your feedback!   


Monday, September 19, 2016

Start End Title Author(s) Presentation Video
9:00am 12:00 pm Advanced API Programming Pavan Balaji PDF  
1:00 pm 3:00 pm Advanced OpenMP Lars Koesterke and Kent Milfeld PDF  
3:00 pm 3:30 pm Break      
3:30 pm 5:30 pm Ensuring Program Correctness and Optimal Performance on Intel Phi Using Allinea Forge Ryan Hulguin and Beau Paisley PDF  
Techniques Tutorial     
9:00 am 12:00 pm Vectorization Strategies for Intel’s 2nd Generation Intel Xeon® Phi™ Architecture Codenamed Knights Landing Ashish Jha, Vitali Morozov and Jack Deslippe PDF  
1:00 pm 5:00 pm Top Ten Issues for Effectively Utilizing a Large KNL System John Levesque PDF  

Tuesday, September 20, 2016

Start End Title Author(s)  Presentation Video
9:00 am 9:10 am Welcome from the IXPUG2016 Chair David Martin PDF  
9:10 am 9:20 am Welcome from the IXPUG Chair Richard Gerber PDF Video
9:20 am 10:00 am Backwards and Forwards: The Road to Many Core Computing Joe Curley PDF Video
10:00 am 10:30 am ALCF: Overview and Future Thoughts Mike Papka PDF  
11:00 am 12:15 pm Major Sites Updates: NERSC, TACC, ALCF

Richard Gerber, John Cazes and Kalyan Kumaran





1:30 pm 2:30 pm DOE and NIH Partnerships: Cancer and Brain Rick Stevens PDF  
2:30 pm 3:45 pm Early Science with KNL at TACC, ALCF and NERSC Jack Deslippe, Tim Williams and Lars Koesterke PDF Video
4:15 pm 4:45 pm OpenFOAM Optimization on KNL Prasad Pawar, Paul Edwards, Nishant Agrawal, Ravi Ojha and Sonia Rani PDF Video
4:45 pm 5:15 pm Optimizing Particle-In-Cell Codes for Intel Xeon Phi Processors Mathieu Lobet, Henri Vincenti, Jean-Luc Vay and Jack Deslippe PDF Video

Wednesday, September 21, 2016

Start End Title Author(s)  Presentation Video
8:45 am 9:15 am Optimizations of Bspline-based Orbital Evaluations in Quantum Monte Carlo on Multi/Many-core Shared Memory Processors Ye Luo, Amrita Mathuriya, Anouar Benali, Luke Shulenburger and Jeongnim Kim PDF Video
9:15 am 9:45 am Enabling Large-Scale Hybrid Density Functional Theory Based Ab Initio Molecular Dynamics in Condensed-Phase Systems Robert Distasio, Junteng Jia and Alvaro Vazquez-Mayagoitia PDF Video
9:45 am 10:15 am Performance Optimization of Quantum Espresso on KNL Taylor Barnes and Jack Deslippe PDF Video
10:45 am 11:15 am Cache Blocking using Tiling in a Molecular Dynamics Application Benny Mathew and Manoj Nambiar PDF Video
11:15 am 11:45 am Efficient MPI/OpenMP Parallelization of the Hartree-Fock Method on Intel® Xeon Phi Processors Yuri Alexeev, Michael D'Mello, Vladimir Mironov and Alexander Moskovsky PDF Video
11:45 am 11:55 am MILC Staggered Conjugate Gradient Performance on Intel KNL Ruizi Li, Carleton Detar, Douglas Doerfler, Steven Gottlieb, Ashish Jha, Balint Joo, Dhiraj Kalamkar and Doug Toussaint PDF Video
11:55 am 12:05 pm Optimizing Magnetic Fusion PIC Code XGC1 for Xeon Phi Tuomas Koskela PDF  
12:05 pm 12:15 pm Scaling the Performance of a FDFD Geophysical-imaging Application to Multi-node KNL Clusters Tareq Malas, Thorsten Kurth and Jack Deslippe PDF  
1:30 pm 2:00 pm Accurate and Efficient Earthquake Simulations on Intel Xeon Phi Josh Tobin, Alexander Breuer, Charles Yount, Alexander Heinecke and Yifeng Cui PDF Video
2:00 pm 2:30 pm Seismic Simulations with Local Time Stepping on Xeon and Xeon Phi Processors Alexander Breuer, Alexander Heinecke and Yifeng Cui PDF Video
2:30 pm 3:00 pm Grid: Structured Cartesian Mesh Library for Quantum Chromodynamics Peter Boyle, Azusa Yamaguchi, Guido Cossu and Antonin Portelli PDF Video
3:30 pm 3:40 pm Enabling High-performance Simulation of Subsurface Flows and Geochemical Processes with Chombo-Crunch on Intel Xeon Phi Knights Landing Andrey Ovsyannikov PDF Video
3:40 pm 3:50 pm Reconstructing Particle Trajectories in High Energy Physics with Xeon and Xeon Phi David Abdurachmanov, Peter Elmer, Giuseppe Cerati, Slava Krutelyov, Steven Lantz, Matthieu Lefebvre, Kevin McDermott, Daniel Riley, Matevz Tadel, Peter Wittich, Frank Wuerthwein and Avi Yagil PDF  
3:50 pm 4:00 pm HACC on the KNL - Porting, Optimizing, and Early Experiences Hal Finkel, Adrian Pope and JD Emberson PDF  
4:00 pm 4:30 pm Optimizing MFDn (a Nuclear Physics CI Code) for KNL Pieter Maris PDF Video
4:30 pm 5:00 pm Boundary Element Method for Manycore Architectures Jan Zapletal and Michal Merta PDF  
Memory Models and Methods     
8:45 am 9:15 am Managing Per Job Reconfiguration of Xeon Phi Knights Landing Clusters Michael Hebenstreit PDF  
9:15 am 9:45 am MCDRAM on 2nd Generation Intel® Xeon Phi™ Processor James Tullos and Karthik Raman PDF  
9:45 am 10:15 am Cache Size on KNL at LANL Phillip Romero PDF  
10:45 am 11:15 am Chroma on Knights Landing Three Ways Balint Joo, Frank Winter, Thorsten Kurth and Jacques Bloch PDF  
11:15 am 11:45 am Tuning Generated Code for KNL James Osborn PDF  
11:45 am 11:55 am Asynchronous Memory Migration on the KNL Swann Perarnau and Kamil Iskra PDF  
11:55 am 12:05 pm Understanding Knight's Landing HIgh Bandwidth Memory Using the STREAM Benchmark Agrima Bahl and Brian Austin PDF  
12:05 pm 12:15 pm Bringing the Customer to the Tech Richard Coffey and Jini Ramprakash PDF  
Programming Tutorial     
1:30 pm 5:00 pm Programming Intel’s 2nd Generation Xeon Phi (Knights Landing) Carlos Rosales-Fernandez, Kent Milfeld and John Cazes PDF  
Optimization Tutorial     
8:45 am 12:15 pm Optimize Your Workload for Memory and SIMD Parallelism on x86 Platforms with Intel® Advisor XE Zakhar Matveev and Michael D'mello PDF  
1:30 pm 5:30 pm Optimizing Codes Using the Roofline Model Jack Deslippe, Zakhar Matveev, Richard Gerber, Brandon Cook, Tuomas Koskela, Mathieu Lobet and Tareq Males PDF  

Thursday, September 22, 2016

Programming and Visualization Tutorial     
Start End Title Author(s) Presentation Video
9:00 am 9:30 am Heterogeneous Programming of Intel Xeon and Intel Xeon Phi with Intel TBB Flow Graph Evgeny Fiksman, Michael Voss and Sergey Vinogradov PDF Video
9:30 am 10:00 am LLVM and Clang on the KNL Hal Finkel PDF Video
10:00 am 10:10 am MPI + hStreams in NEMO5: Partitioning Xeon Phi Xinchen Guo, Daniel Lemus, Daniel Mejia, Jim Fonseca, Gerhard Klimeck and Tillmann Kubis PDF  
10:10 am 10:20 am Process and Thread Affinity with MPI/OpenMP on KNL Helen He PDF Video
10:20 am 10:30 am Effective OpenMP Implementations on Intel's Knights Landing Yuliana Zamora PDF  
11:00 am 11:30 am Visualization with OSPRay: Research and Production Aaron Knoll and Ingo Wald PDF Video
11:30 am 11:45 am Visualization with vl3. Now on the CPU Silvio Rizzi, Joseph Insley and Aaron Knoll PDF Video
1:00 pm 2:00 pm Performance Tuning on KNL with Intel® Parallel Studio XE 2017 Cluster Edition James Tullos PDF Video
Working Group Meeting     
2:00 pm 3:00 pm Joint Working Group Meetings John Pennycook and WG members PDF  

 Printable Agenda for PDFs: MondayTuesdayWednesdayThursday

 Slides: IXPUG Presentation Repository

 Video Broadcast: Webcast Schedule

Streaming Video Links: IXPUG Tuesday, IXPUG Wednesday, IXPUG Thursday

IXPUG2016 Program Committee:

David Martin (chair) Argonne National Laboratory
Richard Gerber (vice-chair) Lawrence Berkeley National Laboratory
Gilles Civario Dell
Ryan Coleman Sandia National Laboratories
Jeanine Cook Sandia National Laboratories
Douglas Doerfler (tutorial chair) Lawrence Berkeley National Laboratory
Melyssa Fratkin Texas Advanced Computing Center (TACC)
Rahul Hardikar Indian Institute of Science Education and Research (IISER), Pune
Steve Leak Lawrence Berkeley National Laboratory
Michael Lysaght Irish Centre for High End Computing (ICHEC)
Kent Milfeld Texas Advanced Computing Center (TACC)
John Pennycook Intel Corporation
Abhinav Sarje Lawrence Berkeley National Laboratory
Lisa Smith Intel Corporation
Thomas Steinke Zuse Institute Berlin
Estela Suarez Forschungszentrum Juelich
Srinath Vadlamani ParaTools, Inc.
Jerome Vienne Texas Advanced Computing Center (TACC)
Georg Zitzlsberger Intel Corporation
Important Dates: 
Abstract Submission Deadline 18 August 2016
Abstracts reviewed by IXPUG Committee 19 - 26 August 2016
Acceptance Notification  29 August 2016

Final Presentations due from Speakers

upload to https://easychair.org/conferences/?conf=ixpug2016

16 September 2016
Final Agenda published 9 September 2016

Meeting Location:
Argonne National Laboratory, TCS Conference Center, Argonne, IL 60439. Argonne map: http://www.anl.gov/downloads/map-Argonne

Event Details

Event Date

Sep 19-22, 2016