ISC 2023 IXPUG Workshop

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ISC 2023 IXPUG Workshop

ISC 2023 IXPUG Workshop WITH Proceedings "Communication, I/O, and Storage at Scale on Next-Generation Platforms"

Date: May 25, 2023 9:00 a.m. - 6:00 p.m. full-day workshop WITH proceedings

Location: In-person at ISC 2023, Hamburg, Germany – room location to be announced soon

Call for Submissions: March 31, 2023 AoE https://easychair.org/cfp/ISC-2023-IXPUG-Workshop

Registration: https://www.isc-hpc.com/

Event Description:

The workshop intends to attract system architects, code developers, research scientists, system providers, and industry luminaries who are interested in learning about the interplay of next-generation hardware and software solutions for communication, I/O, and storage subsystems tied together to support HPC and data analytics at the systems level, and how to use them effectively. The workshop will provide the opportunity to assess technology roadmaps to support AI and HPC at scale, sharing users’ experiences with early-product releases and providing feedback to technology experts. The overall goal is to make the ISC community aware of the emerging complexity and heterogeneity of upcoming communication, I/O and storage subsystems as part of next-generation system architectures and inspect how these components contribute to scalability in both AI and HPC workloads.

The workshop will pursue several objectives: (1) Develop and provide a holistic overview of next-generation platforms with an emphasis on communication, I/O, and storage at scale, (2) Showcase application-driven performance analysis with various HPC fabrics, (3) Present early experiences with emerging storage concepts like object stores using next-generation HPC fabrics, (4) Share experience with performance tuning on heterogeneous platforms from multiple vendors, and (5) Be a forum for sharing best practices for performance tuning of communication, I/O, and storage to improve application performance at scale and any challenges. 

Workshop Format:

The workshop will have a keynote, full (30 min) talks and lightning talks (10-15 min). While in-person presentations are preferred, pre-recorded videos will be allowed as presentation in exceptional cases.

Call for Submissions:

The submission process will close on March 31, 2023 AoE. All submitters should provide content that represents an Extended Abstract, max. 6-12 pages in LNCS format via the IXPUG EasyChair website. Notifications will be sent to submitters by April 17, 2023 AoE.

Topics of Interest are (but not limited to):

  • Holistic view on performance of next-generation platforms (with emphasis on communication, I/O, and storage at scale)
  • Application driven performance analysis on inter-node and intra-node HPC fabrics
  • Software-defined networks in HPC environments
  • Experiences with with emerging scalable storage concepts, e.g., object stores using next-generation HPC fabrics
  • Performance tuning on heterogeneous platforms from multiple vendors including impact of I/O and storage
  • Performance and portability using network programmable devices (DPU, IPU)
  • Best practice solutions for performance tuning of communication, I/O, and storage to improve application performance at scale and any challenges.

Keywords:

high-performance fabrics, data and infrastructure processing units, scalable object stores as HPC storage subsystems, heterogeneous data processing

Review Process:

All submissions within the scope of the workshop will be peer-reviewed and will need to demonstrate the high quality of the results, originality and new insights, technical strength, and correctness. We apply a standard single-blind review process, i.e., the authors will be known to reviewers. The assignment of reviewers from the Program Committee will avoid conflicts of interest.

Important Dates:

  • Call for Papers/Contributions: Feb 24, 2023
  • Deadline for submissions: March 31, 2023
  • Acceptance notification: April 17, 2023
  • Camera ready presentation: May 22, 2023
  • Workshop date: May 25, 2023

Organizers:

  • R. Glenn Brook, Cornelis Networks
  • Nalini Kumar, Intel Corporation
  • David Martin, Argonne Leadership Computing Facility
  • Amit Ruhela, Texas Advanced Computing Center
  • Thomas Steinke, Zuse Institute Berlin

Program Committee:

  • R. Glenn Brook, Cornelis Networks
  • Clayton Hughes, Sandia National Laboratories
  • Andrey Kudryavtsev, Intel Corporation
  • Nalini Kumar, Intel Corporation
  • Johann Lombardi, Intel Corporation
  • David Martin, Argonne National Laboratory
  • Christopher Mauney, Los Alamos National Laboratory
  • Kelsey Prantis, Intel Corporation

General questions should be sent to This email address is being protected from spambots. You need JavaScript enabled to view it.