August 2020 Newsletter

Events

Are you working on your submission for the IXPUG Annual Conference 2020? The abstracts deadline is coming up soon! We want to hear from all IXPUG members about your successes and challenges with multicore methods, tools, etc. Submit your abstract and invite your colleagues to join Intel and industry experts from around the world as we gather virtually to share results, lessons learned, and future plans. More information at the links below.

Call for presentations deadline: August 21, 2020 (updated!) via EasyChair

Conference dates: October 13–16, 2020

Location: Online, virtually hosted by TACC

Event details: https://www.ixpug.org/ixpug-2020

Resources

• Blog: Harnessing the Power of a Heterogeneous Computing Future by Jeffrey S. McVeigh, VP, Intel Architecture, Graphics and Software and GM, Data Center XPU Products & Solutions and Srinivas Chennupaty, VP & CTO, Intel Architecture, Graphics, Software and GM, XPU Architecture Technology Roadmap.
• On-demand course: Learn the essentials of DPC++ – Data Parallel C++ (DPC++) is a high-level language designed for data parallel programming productivity. This hands-on course is for developers who want to learn the basics of DPC++ for heterogeneous computing (CPU, GPU, FPGA, Accelerators, etc.) and will walk you through the process step-by-step using sample code that will teach you how to develop, test, and run your own oneAPI code within the Intel® DevCloud for oneAPI environment.
• Article: Using OpenMP Accelerator Offload for Programming Heterogeneous Architectures – OpenMP offload support, now provided as part of the Intel oneAPI Base Toolkit, lets you easily migrate compute-intensive parts of your application to accelerators. This article outlines the methodology to identify code regions that are suitable for offloading, along with the appropriate OpenMP offload pragmas, then using profiling and tuning to achieve optimal performance.
• Article: Accelerate Your scikit-learn Applications: Faster Experimentation with Predictable Behavior – The Intel Distribution for Python (IDP), part of the Intel AI Analytics Toolkit, includes an optimized scikit-learn that accelerates a selection of common estimators (e.g., logistic regression, singular value decomposition, principal component analysis). These functions are built on top of the Intel Data Analytics Acceleration Library (DAAL) so they achieve performance close to that equivalent C++ programs. The DAAL-powered estimators are implemented in the daal4py package. This article invites you to try accelerating your scikit-learn workloads with daal4py and Intel AI Analytics Toolkit to see the performance improvements for yourself.
• The Intel HPC + AI Pavilion is a virtual content hub containing podcasts, tech talks, and more on recent advancements including the HPC community’s response to the COVID-19 pandemic.
• Looking for presentations from our past Workshops, Meetings, and BOFs? Check the IXPUG Resources page for a searchable repository of slides and recordings from all of our events.

Webinars and Podcasts

• AI Analytics PART 2: Enhance Deep Learning Workloads on 3rd Gen Intel® Xeon® Scalable Processors – Louie Tsai, Software Engineer, Intel Corporation (Wednesday, August 19, 2020 | 9:00-10:00AM PT)
• AI Analytics PART 3: Walk Through the Steps to Optimize End-to-End Machine Learning Workflows – Meghana Rao, oneAPI and AI Evangelist, and Anant Sinha, Software Applications Engineer, Intel Corporation (Wednesday, September 2, 2020 | 9:00-10:00AM PT)
• Find CPU and GPU Performance Headroom Using Roofline Analysis – Cedric Andreolli, Technical Consulting Engineer, Intel Corporation (Wednesday, September 9, 2020 | 9:00-10:00AM PT)
• "Migrating Your Existing CUDA Code to DPC++" – learn from Edward Mascarenhas, Senior Strategic Planner in the Intel Architecture, Graphics and Software organization and Sunny Gogar, Software Applications Engineer at Intel, about best practices for using a one-time migration tool that migrates CUDA applications into standards-based Data Parallel C++ (DPC++) code. Includes overview, real world examples, and demo of migration steps.
• "A Shift to Modern C++ Programming Models" – Alice Chan, VP and GM of Compiler Engineering at Intel, and Hal Finkel, Lead for Compiler Technology and Programming Languages at Argonne National Lab, discuss the shift to modern C++ programming models, the cross-industry oneAPI initiative, DPC++, and the need for portable performance.

About IXPUG

• IXPUG is an independent users group whose mission is to provide a forum for the free exchange of information that enhances the usability and efficiency of scientific and technical applications running on HPC, AI, and data analytics systems using advanced Intel technologies. IXPUG is administered by representatives of member sites that operate large Intel-based HPC systems.