2020 IXPUG Annual Meeting

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2020 IXPUG US Annual Meeting 

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Experts from around the world are invited to join us online 
for the 

IXPUG 2020 Annual Meeting

(Virtually Hosted by TACC) 


Location: Online - Registration and Zoom information below
Date: October 13-16, 2020

Register now - Click here! Registration is free. 

After you register for the conference, please register through this link to join the Zoom Webinar. The zoom link will then be the same all week. 



Tuesday, October 13 -- All times listed for Austin/CDT (UTC -5) 
Start End Title Author Presentation Video
10:00 10:15 Welcome

Melyssa Fratkin, IXPUG Secretary
Stephen Harrell & Amit Ruhela, Meeting Co-Chairs

10:15 11:00 Keynote: The landscape of modern parallel programming using Open Standards Michael Wong    
11:00 11:30 Intel® DPC++ Compatibility Tool – Porting SPECFEM3D GLOBE to DPC++ Sunny Gogar, Konstantinos Krommydas, Rama Kishan V Malladi and Philippe Thierry    
11:30 12:00 Custom-Precision Mathematical Library Explorations for Code Profiling and Optimization David Defour, Pablo de Oliveira Castro, Matei Istoan and Eric Petit    
12:00 12:30 Break       
12:30 13:00 Simulating quantum algorithms on HPC systems: a performance perspective Luigi Iapichino and Fabio Baruffa    
13:00 13:30 User-space thin file system coupled with an ultra-fast and low-latency IO stack as an alternative for use by database storage engines Jan Lisowiec    
13:30 14:00 Optane PMem as an Enabler for Large DNN Models with Homomorphic Encryption Guillermo Lloret-Talavera, Marc Jorda, Harald Servat, Fabian Boemer, Chetan Chauhan, Shigeki Tomishima, Nilesh N. Shah and Antonio J. Peña    
14:00  14:15 Break       
14:15 15:15 Lightning Talks (15 Mins each)       
    Overlapping communication and computation using the Intel MPI library's asynchronous progress control Sebastian Ohlmann, Fabio Baruffa and Markus Rampp    
    Mixed-Precision Arithmetic for 3DGAN to Simulate High Energy Physics Detectors John Osorio Rios, Adrià Armejach, Gulruk Khattak, Eric Petit, Sofia Vallecorsa and Marc Casas    
    Porting NAQMD kernels to GPU via OpenMP Offload Pankaj Rajak, Ye Luo, Ken-Ichi Nomura and Aiichiro Nakano    
    Performance analysis of OpenMP Offload on IntelGen9 Neil Mehta, Rahul Gayatri, Yasaman Ghadar and Jack Deslippe    
15:15 16:15 Tutorial: Accelerating Deep Learning workloads by using Intel(R) AI Analytics Toolkit and 3rd generation Xeon Scalable processors Louie Tsai     
16:15   Closing Remarks      
 Wednesday, October 14 -- All times listed for Austin/CDT (UTC -5) 
Start End Title Author Presentation Video
10:00 10:15 Welcome Stephen Harrell & Amit Ruhela, Meeting Co-Chairs    
10:15 11:00 Keynote: How HPC developers are using SYCL need to deal with data movement Michael Wong and Rod Burns    
11:00 11:30 Characterizing simulation and machine learning workloads Chris Lishka       
11:30 12:00 SYCL Performance and Portability Kumudha Narasimhanm    
12:00 12:30 Break      
12:30 12:45 Lattice QCD on CPU and GPU with OpenMP Patrick Steinbrecher    
12:45 14:00 Site Updates: TACC, ZIB, Argonne, Hartree Center, University of Tsukuba


John Cazes, TACC
Thomas Steinke, ZIB
David Martin, Argonne
Luke Mason, Hartree Center
Taisuke Boku, University of Tsukuba

14:00 14:15 Break      
14:15 15:15 Lightning Talks (15 minutes each)      
    A geometric multigrid method kernel on Intel GPU with Performance Portable Programming Models Jaehyuk Kwack    
    From CUDA to DPC++ back to Nvidia GPUs... and FPGAs - An oneAPI case study with the tsunami simulation easyWave Steffen Christgau and Marius Knaust     
    No Instruction Computing Using Pointer and Operation in Registers for Adaptable Architecture Nagi Mekhiel    
    Simple use of oneMKL for high performance Matthew Cordery, Dahai Guo, Michael D'Mello    
15:15 16:15 Tutorial: Traditional Machine Learning with oneDAL and XGBoost*  Rachel Oberman    
16:15   Closing Remarks      


  Thursday, October 15 -- All times listed for Austin/CDT (UTC -5) 

Start End Title Author Presentation Video
10:00 10:15 Welcome Stephen Harrell & Amit Ruhela, Meeting Co-Chairs    
10:15 12:00 Tutorial: Performance Tuning and Best Practices to leverage Intel MPI on Multicore Processors Amit Ruhela    
12:00 12:30 Break      
12:30 14:00

Tutorials: OneAPI/ DPC++ Essential Series hands on (Through Friday)

oneAPI Intro Module: (This module is used to introduce oneAPI, DPC++ Hello World and Intel DevCloud)

DPC++ Program Structure: (Classes - device, device_selector, queue, basic kernels and ND-Range kernels, Buffers-Accessor memory model, DPC++ Code Anatomy)

Praveen Kundurthy    
14:00 14:15 Break      
14:15 15:15 Tutorial: DPC++ New Features - Unified Shared Memory (USM), Sub-Groups (Intel oneAPI DPC++ Library -Usage of oneDPL,  Buffer Iterators and oneDPL with USM ) Praveen Kundurthy    
15:15   Closing Remarks      


 Friday, October 16 -- All times listed for Austin/CDT (UTC -5) 


Start End Title Author Presentation Video
10:00 10:15 Welcome Stephen Harrell & Amit Ruhela, Meeting Co-Chairs    
10:15 11:30 Tutorial: Migration of GPGPU Applications to DPC++ with Lab - Compatibility tool  Edward Mascarenhas and Sunny Gogar    
11:30 12:00 Break      
12:00 13:30 Tutorial: Running DPC++ code on GPGPU  Ruyman Reyes and Stuart Adams    
13:30 13:45 Break      
13:45 14:30 Tutorial: Cache-Aware Roofline Model: Performance, Power and Energy-Efficiency Aleksandar Ilic    
14:30 15:30 Tutorial: Profile DPC++ and GPU Workload Performance-VTune, Advisor, Roofline analysis  Vladimir Tsymbal    
15:30 15:45 Break      
15:45 16:45 Tutorial: FPGA offload on DPC++ Ricardo Menotti    
16:45   Conference Closing Remarks      


Just Announced! oneAPI Bring-Your-Own-Code (BYOC) Workshop

Have a code that will benefit from heterogenous hardware? In this workshop on Monday, October 19th 8:00AM-12:00PM PT (10:00AM-2:00PM CT) you will have an opportunity to work directly with oneAPI experts to make the code heterogenous. Register via Webex HERE. Participants present their workload and instructors answer questions. Each team gets half an hour and follow up sessions scheduled individually as needed based on topics below: 

DPC++ essentials – Praveen Kundurthy and Rakshit Krishnappa
DPCT – Sunny Gogar and Edward Mascarenhas
DPC++ GPGPU – Ruyman Reyes
Advisor – Vladimir Tsymbal and Prof Aleksandar Ilic
FPGA – Ricardo Menotti
AI/oneDAL/XGBoost – Louie Tsai, Rachael Oberman

We will consider BYOC workshop successful if we are able to help you in porting and tuning of the participants’ codes, either during the workshop or up to two weeks after the workshop.

Call for Presentations:

This Intel eXtreme Performance User Group (IXPUG) conference is focused on all aspects of adopting and employing state-of-the-art technologies and practices for optimal application execution. This includes accelerators (e.g., co-processors, FPGAs, GPUs), as well as topics related to system hardware beyond the processor (memory, interconnects, etc.), software tools, programming models, HPC workloads, troubleshooting, and more — all with a focus on Intel platforms. The conference will provide an interactive experience, organized around key themes associated with high-performance computing, data analytics, artificial intelligence (machine learning and deep learning), cloud computing, and more. The conference will feature keynote presentations, invited expert talks, 30-minute technical sessions, 10-to-15-minute lightning talks, and two-hour hands-on tutorials. Speakers come from a wide variety of HPC organizations and share their real-world experiences. Attendees will encounter an open forum, through which Intel and renowned industry experts will share best practices and techniques for maximizing software productivity and efficiency. The conference will provide an opportunity to share experiences in leveraging Intel architectures and technologies with all attendees, including expert software developers, scientists, researchers, academics, systems analysts, students, and end-users, etc. The challenges surrounding application performance and scalability will be covered across at all levels, including tuning and optimization of diverse sets of applications on large-scale HPC systems.
Abstract Submission Guidelines:
A short abstract should be submitted by August 21, 2020 (updated!) via EasyChair and the content should reflect the topics of interest that are listed below. All final presentations are due by October 9, 2020. We would like you to include keywords that pertain to the techniques, Intel products, and associated domains that pertain to your technical work. Please see the full list below:
Techniques:  Artificial Intelligence (Machine Learning/Deep Learning), Algorithms & Methods, Compiler Flags, Software Environment & Tools, Libraries & Tools, Parallel- Programming (Communications, Thread & Process Management Experience, All), Multi-node, Memory Management, Vectorization, etc.
Products: Intel® Xeon Scalable processor, Intel® Omni Path Fabric, Intel® FPGA, Intel® SSDs/NVMe Solutions, Intel® Lustre Software and DAOS, Visualization Technology, Intel® SW Tools, OneAPI, Intel Xe graphics, Intel Processor Graphics 
Domains: Astrophysics, Bioinformatics, Chemistry, Climate & Weather, Computational Fluid Dynamics, Data Analytics, Energy/Oil & Gas, Financial Services, Geophysics, Life Sciences, Material Science, Medical imaging, Molecular Dynamics, Nanotechnology, Physics, Visualization, High Energy Physics, etc.
Abstract Topics of Interest:
  • Implications of workload behavior on system design at extreme scale (Power, Reliability, Scalability, Performance, Processor Design, Memory System, I/O)

  • Software environments and tools for computing at extreme scale (Instrumentation, Debugging/Correctness, Thread and Process Management, Libraries and Language Development)
  • Experience using extreme scale systems: Usability, In-situ Visualization, Programming Challenges, Algorithms and Methods, etc.
  • Application characterization on emerging technologies: Novel Memories (NVM), processors (Intel® Xeon Scalable processor, Intel® FPGA, etc.) 


Important Dates (Updated!):
Abstract Submission Deadline  August 21  2020
Abstracts Reviewed by IXPUG Committee  August 24-September 11 2020
Acceptance Notification  September 17 2020
Agenda Posted to IXPUG Website  September 21 2020
Final Presentations Due from Speakers  October 9 2020
IXPUG Sessions  October 13-16 2020


IXPUG 2020 Program Committee:

Stephen Harrell (co-Chair) Texas Advanced Computing Center (TACC)
Amit Ruhela (co-Chair) Texas Advanced Computing Center (TACC)
Richard Gerber NERSC/Lawrence Berkeley National Laboratory
Clayton Hughes Sandia National Laboratories
Nalini Kumar Intel Corporation
Ying Wai Li Los Alamos National Laboratory
David Martin Argonne National Laboratory
Christopher Mauney Los Alamos National Laboratory
Anna Pietarila Graham Los Alamos National Laboratory
Thomas Steinke Zuse Institute Berlin
R. Glenn Brook University of Tennessee Knoxville