ISC 2026 IXPUG Workshop

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Sixth workshop on Communication, I/O, and Storage at Scale on Next-Generation Platforms – Scalable Infrastructures

ISC 2026 IXPUG Workshop

Workshop Date: June 26, 2026

Location: In-person at ISC 2026, Hamburg, Germany

Event Description: 

Next-generation HPC platforms have to deal with increasing heterogeneity in their subsystems. These subsystems include internal high-speed fabrics for inter-node communication; storage system integrated with programmable data processing units (DPUs) and infrastructure processing units (IPUs) to support software-defined networks; traditional storage infrastructures with global parallel POSIX-based filesystems complemented with scalable object stores; and heterogeneous compute nodes configured with a diverse spectrum of CPUs and accelerators (e.g., GPU, FPGA, AI processors) having complex intra-node communication.

The workshop intends to attract system architects, code developers, research scientists, system providers, and industry luminaries who are interested in learning about the interplay of next-generation hardware and software solutions for communication, I/O, and storage subsystems tied together to support HPC and data analytics at the systems level, and how to use them effectively. The workshop will provide the opportunity to assess technology roadmaps to support AI and HPC at scale, sharing users’ experiences with early-product releases and providing feedback to technology experts. The overall goal is to make the ISC community aware of the emerging complexity and heterogeneity of upcoming communication, I/O, and storage subsystems as part of next-generation system architectures and inspect how these components contribute to scalability in both AI and HPC workloads. 

Workshop Format: 

The workshop will have a keynote, full (30 min) talks and lightning talks (10-15 min). While in-person presentations are preferred, pre-recorded videos will be allowed as presentations in exceptional cases.

Call for Submissions: 

The submission process will close on March 13, 2026, AoE. All submitters should provide content that represents an Extended Abstract, max. 6-12 pages in LNCS format via the ISC Submisions Portal. Notifications will be sent to submitters by April 10, 2026, AoE. The page limit is 12 pages for each paper, which includes a bibliography and appendices, with two possible extra pages after the review to address the reviewer’s comments. The page limit includes bibliography and appendices.

Topics of Interest are (but not limited to): 

  • Holistic view on performance of next-generation platforms (with emphasis on communication, I/O, and storage at scale)
  • Application-driven performance analysis with various HPC fabrics
  • Software-defined networks in HPC environments
  • Experiences with emerging scalable storage concepts, e.g., object stores using next-generation HPC fabrics
  • Performance tuning on heterogeneous platforms from multiple vendors including impact of I/O and storage
  • Performance and portability using network programmable devices (DPU, IPU)
  • Best practice solutions for application programming with complex communication, I/O, and storage at scale

Keywords: 

high-performance fabrics, data and infrastructure processing units, scalable object stores as HPC storage subsystems, heterogeneous data processing, holistic system view on scalable HPC infrastructures

Review Process: 

All submissions within the scope of the workshop will be peer-reviewed and will need to demonstrate the high quality of the results, originality and new insights, technical strength, and correctness. We apply a standard single-blind review process, i.e., the authors will be known to reviewers. The assignment of reviewers from the Program Committee will avoid conflicts of interest.

Important Dates: 

  • Deadline for submissions: Friday, March 13, 2026
  • Final acceptance notification: Wednesday, April 10, 2026
  • Camera-ready submission deadline (For authors of workshop papers): Tuesday, May 26, 2026
  • Camera-ready presentation: Friday, June 19, 2026
  • Workshop day: Friday, June 26, 2026, 9:00 a.m. – 6:00 p.m (to be confirmed for morning or afternoon slot).

Organizers: 

  • Steffen Christgau, Zuse Institute Berlin
  • David Martin, Argonne Leadership Computing Facility, Argonne National Laboratory
  • Amit Ruhela, Texas Advanced Computing Center (TACC), The University of Texas at Austin
  • Hatem Ltaief, King Abdullah University of Science & Technology

Program Committee: 

  • R. Glenn Brook, Cornelis Networks
  • Toshihiro Hanawa, The University of Tokyo
  • Clayton Hughes, Sandia National Laboratories
  • Nalini Kumar, Intel Corporation
  • James Lin, Shanghai Jiao Tong University
  • Hatem Ltaief, King Abdullah University of Science & Technology
  • David Martin, Argonne Leadership Computing Facility, Argonne National Laboratory
  • Christopher Mauney, Los Alamos National Laboratory
  • John Pennycook, Intel Corporation
  • Amit Ruhela, Texas Advanced Computing Center (TACC), The University of Texas at Austin

Contact:

Please contact This email address is being protected from spambots. You need JavaScript enabled to view it. with any general questions.