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The high-performance computing (HPC) ecosystem increasingly supports heterogeneous architectures and customization. Field programmable gate arrays (FPGA) are among the options being considered due to their ability to both adapt to individual workloads and serve as prototype vehicles for application-specific accelerators. However, adoption has been limited due to the difficulty in programming these devices. To mitigate this, vendors are introducing frameworks based on embedded domain specific languages (eDSLs), such as SYCL. This work takes the first step in evaluating one of these new DSLs, DPC++, using DOE proxy applications to identify programmability gaps and performance on Intel FPGAs. Initial testing is being done with the MiniAMR application from the Mantevo suite, focusing on the 7-point stencil.

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IXPUG Mid-Year Workshop 2021


FPGA Evaluation,oneAPI,Mantevo,SYCL,DPC++

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