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IXPUG at ISC 2024

Communication, I/O, and Storage at Scale on Next-Generation Platforms – Scalable Infrastructures

SC24 IXPUG Workshop

Workshop Date/Time: To be announced soon

Location: In-person at SC24, Atlanta, Georgia

Event Description:

The workshop is a continuation of our effort to bring together HPC users, researchers, and developers from across the globe to share experiences around topics most pertinent to the future of large heterogeneous HPC systems.

Next-generation HPC platforms have to deal with increasing heterogeneity in their subsystems. These subsystems include internal high-speed fabrics for inter-node communication; storage system integrated with programmable data processing units (DPUs) and infrastructure processing units (IPUs) to support software-defined networks; traditional storage infrastructures with global parallel POSIX-based filesystems complemented with scalable object stores; and heterogeneous compute nodes configured with a diverse spectrum of CPUs and accelerators (e.g., GPU, FPGA, AI processors) having complex intra-node communication.

The workshop will pursue multiple objectives, including: (1) develop and provide a holistic overview of next-generation platforms with an emphasis on communication, I/O, and storage at scale, (2) showcase application-driven performance analysis with various HPC network fabrics, (3) present experiences with emerging storage concepts like object stores and all-flash storage, (4) share experiences with performance tuning on heterogeneous platforms from multiple vendors, and (5) share best practices for application programming with complex communication, I/O, and storage at scale.

The workshop intends to attract system architects, code developers, research scientists, system providers, and industry luminaries who are interested in learning about the interplay of next-generation hardware and software solutions for communication, I/O, and storage subsystems tied together to support HPC and data analytics at the systems level, and how to use them effectively. The workshop will provide the opportunity to assess technology roadmaps to support AI and HPC at scale, sharing users’ experiences with early-product releases and providing feedback to technology experts. The overall goal is to make the SC community aware of the emerging complexity and heterogeneity of upcoming communication, I/O and storage subsystems as part of next-generation system architectures and inspect how these components contribute to scalability in both AI and HPC workloads.

Workshop Format:

Full-day workshop. The workshop program will feature two invited talks from Industry as well as academia, several technical talks, and a few shorter ’lightning talks’ to feature late-breaking work in this area.

Call for Submissions:

To be announced soon.

Topics of Interest Are (but Not Limited To):

  • Holistic view on performance of next-generation platforms (with emphasis on communication, I/O, and storage at scale)
  • Application-driven performance analysis with various HPC fabrics
  • Software-defined networks in HPC environments
  • Experiences with emerging scalable storage concepts, e.g., object stores using next-generation HPC fabrics
  • Performance tuning on heterogeneous platforms from multiple vendors including impact of I/O and storage
  • Performance and portability using network programmable devices (DPU, IPU)
  • Best practice solutions for application programming with complex communication, I/O, and storage at scale

Keywords:

High-performance fabrics, data and infrastructure processing units, scalable object stores as HPC storage subsystems, heterogeneous data processing on accelerators, holistic system view on scalable HPC infrastructures

Review Process:

All submissions within the scope of the workshop will be peer-reviewed and will need to demonstrate high quality results, originality and new insights, technical strength, and correctness. We will apply a standard single-blind review process, i.e., the authors will be known to reviewers. The assignment of reviewers from the Program Committee will avoid conflicts of interest.

Important Dates:

  • Deadline for submissions: August 23, 2024
  • Acceptance notification: September 6, 2024
  • Camera ready presentation: September 25, 2024
  • Workshop date: To be announced soon

Organizers:

  • Glenn Brook, Cornelis Networks
  • Steffen Christgau, Zuse Institute Berlin
  • Clayton Hughes, Sandia National Laboratories
  • Nalini Kumar, Intel Corporation
  • Hatem Ltaief, King Abdullah University of Science & Technology
  • David Martin, Argonne National Laboratory
  • Christopher Mauney, Los Alamos National Laboratory
  • Amit Ruhela, Texas Advanced Computing Center (TACC)

Program Committee:

  • Aksel Alpay, Heidelberg University
  • Glenn Brook, Cornelis Networks
  • Steffen Christgau, Zuse Institute Berlin
  • Toshihiro Hanawa, The University of Tokyo
  • Clayton Hughes, Sandia National Laboratories
  • Nalini Kumar, Intel Corporation
  • James Lin, Shanghai Jiao Tong University
  • Hatem Ltaief, King Abdullah University of Science & Technology
  • David Martin, Argonne National Laboratory
  • Christopher Mauney, Los Alamos National Laboratory
  • Amit Ruhela, Texas Advanced Computing Center (TACC)

Contact:

Please contact This email address is being protected from spambots. You need JavaScript enabled to view it. with any general questions.